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authorTom Rini <trini@konsulko.com>2019-12-18 07:20:19 -0500
committerTom Rini <trini@konsulko.com>2019-12-18 07:20:19 -0500
commitc0912f9bbfb26dd03d189953678691b799d35b6e (patch)
treef879600cd26b8d4678a174854b623941e5dc2ada /arch/x86/include/asm/arch-apollolake/uart.h
parent533c9f5714bdba79dc6f2629284d4c1a08a611d1 (diff)
parenta1d6dc3f84071f05574044f337dbdca70fae495d (diff)
Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next
- Various x86 common codes updated for TPL/SPL - I2C designware driver updated for PCI - ICH SPI driver updated to support Apollo Lake - Add Intel FSP2 base support - Intel Apollo Lake platform specific drivers support - Add a new board Google Chromebook Coral
Diffstat (limited to 'arch/x86/include/asm/arch-apollolake/uart.h')
-rw-r--r--arch/x86/include/asm/arch-apollolake/uart.h20
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/x86/include/asm/arch-apollolake/uart.h b/arch/x86/include/asm/arch-apollolake/uart.h
new file mode 100644
index 0000000000..d4fffe6525
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/uart.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#ifndef _ASM_ARCH_UART_H
+#define _ASM_ARCH_UART_H
+
+/**
+ * apl_uart_init() - Set up the APL UART device and clock
+ *
+ * This enables the PCI device, sets up the MMIO region and turns on the clock
+ * using LPSS.
+ *
+ * The UART won't actually work unless the GPIO settings are correct and the
+ * signals actually exit the SoC. See board_debug_uart_init() for that.
+ */
+int apl_uart_init(pci_dev_t bdf, ulong base);
+
+#endif