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| author | Tom Rini <trini@konsulko.com> | 2021-01-31 08:49:53 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-01-31 08:49:53 -0500 |
| commit | 242ef48ea76ae13ac6357cc50aae01eb7a46bfef (patch) | |
| tree | 18105866b6063eddcc7ddb0530c002fadc377b3b /arch/x86/cpu | |
| parent | 76404f86a24aa28efc26a296bf6ab9d697c60b9f (diff) | |
| parent | f84eda89e5970ef513fe64ba8e8d977788c44dca (diff) | |
Merge tag 'dm-pull-30jan21' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm
tpm fixes for coral
binman fixes support for symbols in sub-sections
support for additional cros_ec commands
various minor fixes / tweaks
Diffstat (limited to 'arch/x86/cpu')
| -rw-r--r-- | arch/x86/cpu/i386/cpu.c | 2 | ||||
| -rw-r--r-- | arch/x86/cpu/start.S | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index 7517b756f4..6fa0f4d32b 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -175,7 +175,7 @@ void arch_setup_gd(gd_t *new_gd) * Per Intel FSP external architecture specification, before calling any FSP * APIs, we need make sure the system is in flat 32-bit mode and both the code * and data selectors should have full 4GB access range. Here we reuse the one - * we used in arch/x86/cpu/start16.S, and reload the segement registers. + * we used in arch/x86/cpu/start16.S, and reload the segment registers. */ void setup_fsp_gdt(void) { diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 3b6ed37bc0..3d0d95295f 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -77,7 +77,7 @@ _start: lgdt gdt_ptr2 #endif - /* Load the segement registers to match the GDT loaded in start16.S */ + /* Load the segment registers to match the GDT loaded in start16.S */ movl $(X86_GDT_ENTRY_32BIT_DS * X86_GDT_ENTRY_SIZE), %eax movw %ax, %fs movw %ax, %ds |