Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next

- Various x86 common codes updated for TPL/SPL
- I2C designware driver updated for PCI
- ICH SPI driver updated to support Apollo Lake
- Add Intel FSP2 base support
- Intel Apollo Lake platform specific drivers support
- Add a new board Google Chromebook Coral

1 files changed, 73 insertions, 0 deletions

diff --git a/arch/x86/cpu/intel_common/fast_spi.c b/arch/x86/cpu/intel_common/fast_spi.c
new file mode 100644
index 0000000000..a6e3d0a5bf
--- /dev/null
+++ b/arch/x86/cpu/intel_common/fast_spi.c
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/cpu_common.h>
+#include <asm/fast_spi.h>
+#include <asm/pci.h>
+
+/*
+ * Returns bios_start and fills in size of the BIOS region.
+ */
+static ulong fast_spi_get_bios_region(struct fast_spi_regs *regs,
+				      uint *bios_size)
+{
+	ulong bios_start, bios_end;
+
+	/*
+	 * BIOS_BFPREG provides info about BIOS-Flash Primary Region Base and
+	 * Limit. Base and Limit fields are in units of 4K.
+	 */
+	u32 val = readl(&regs->bfp);
+
+	bios_start = (val & SPIBAR_BFPREG_PRB_MASK) << 12;
+	bios_end = (((val & SPIBAR_BFPREG_PRL_MASK) >>
+		     SPIBAR_BFPREG_PRL_SHIFT) + 1) << 12;
+	*bios_size = bios_end - bios_start;
+
+	return bios_start;
+}
+
+int fast_spi_get_bios_mmap(pci_dev_t pdev, ulong *map_basep, uint *map_sizep,
+			   uint *offsetp)
+{
+	struct fast_spi_regs *regs;
+	ulong bar, base, mmio_base;
+
+	/* Special case to find mapping without probing the device */
+	pci_x86_read_config(pdev, PCI_BASE_ADDRESS_0, &bar, PCI_SIZE_32);
+	mmio_base = bar & PCI_BASE_ADDRESS_MEM_MASK;
+	regs = (struct fast_spi_regs *)mmio_base;
+	base = fast_spi_get_bios_region(regs, map_sizep);
+	*map_basep = (u32)-*map_sizep - base;
+	*offsetp = base;
+
+	return 0;
+}
+
+int fast_spi_early_init(pci_dev_t pdev, ulong mmio_base)
+{
+	/* Program Temporary BAR for SPI */
+	pci_x86_write_config(pdev, PCI_BASE_ADDRESS_0,
+			     mmio_base | PCI_BASE_ADDRESS_SPACE_MEMORY,
+			     PCI_SIZE_32);
+
+	/* Enable Bus Master and MMIO Space */
+	pci_x86_clrset_config(pdev, PCI_COMMAND, 0, PCI_COMMAND_MASTER |
+			      PCI_COMMAND_MEMORY, PCI_SIZE_8);
+
+	/*
+	 * Disable the BIOS write protect so write commands are allowed.
+	 * Enable Prefetching and caching.
+	 */
+	pci_x86_clrset_config(pdev, SPIBAR_BIOS_CONTROL,
+			      SPIBAR_BIOS_CONTROL_EISS |
+			      SPIBAR_BIOS_CONTROL_CACHE_DISABLE,
+			      SPIBAR_BIOS_CONTROL_WPD |
+			      SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE, PCI_SIZE_8);
+
+	return 0;
+}