diff options
| author | Simon Glass <sjg@chromium.org> | 2018-10-01 12:22:37 -0600 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2018-10-09 04:40:27 -0600 |
| commit | 590cee8315e94e729493d2ecd8a604bcfbfa7d0e (patch) | |
| tree | 2ac3eacb5e1a1274da1efd3fe34a893d8d978d65 /arch/x86/cpu/coreboot/coreboot.c | |
| parent | 6f1c0430e88396abc8e6a91ab3cc78882c76cb7c (diff) | |
x86: Update mtrr functions to allow leaving cache alone
At present the mtrr functions disable the cache before making changes and
enable it again afterwards. This is fine in U-Boot, but does not work if
running in CAR (such as we are in SPL).
Update the functions so that the caller can request that caches be left
alone.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/cpu/coreboot/coreboot.c')
| -rw-r--r-- | arch/x86/cpu/coreboot/coreboot.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index a6fd3a849a..aaf0d07192 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -55,10 +55,10 @@ static void board_final_cleanup(void) if (top_type == MTRR_TYPE_WRPROT) { struct mtrr_state state; - mtrr_open(&state); + mtrr_open(&state, true); wrmsrl(MTRR_PHYS_BASE_MSR(top_mtrr), 0); wrmsrl(MTRR_PHYS_MASK_MSR(top_mtrr), 0); - mtrr_close(&state); + mtrr_close(&state, true); } if (!fdtdec_get_config_bool(gd->fdt_blob, "u-boot,no-apm-finalize")) { |