diff options
author | Rick Chen <rick@andestech.com> | 2017-12-26 13:55:49 +0800 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2018-01-12 08:05:12 -0500 |
commit | 8bbb2909cbce083f35317d6a7279d02a82f21892 (patch) | |
tree | 70705499ed43435b1cf8e11f4f2cfa75133a64d1 /arch/riscv/lib/cache.c | |
parent | e8e39597a33cc53aacbaf4ef5cae60ed86d6a20a (diff) |
riscv: nx25: lib: Add relative lib funcs to support RISC-V
Add makefile, interrupts.c and boot.c,... functions
to support RISC-V arch.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Signed-off-by: Greentime Hu <green.hu@gmail.com>
Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
Diffstat (limited to 'arch/riscv/lib/cache.c')
-rw-r--r-- | arch/riscv/lib/cache.c | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c new file mode 100644 index 0000000000..948656fdf2 --- /dev/null +++ b/arch/riscv/lib/cache.c @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation <rick@andestech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +void flush_dcache_range(unsigned long start, unsigned long end) +{ +} + +void invalidate_icache_range(unsigned long start, unsigned long end) +{ +} + +void invalidate_dcache_range(unsigned long start, unsigned long end) +{ +} + +void flush_cache(unsigned long addr, unsigned long size) +{ +} + +void icache_enable(void) +{ +} + +void icache_disable(void) +{ +} + +int icache_status(void) +{ + return 0; +} + +void dcache_enable(void) +{ +} + +void dcache_disable(void) +{ +} + +int dcache_status(void) +{ + return 0; +} |