diff options
| author | Samuel Holland <samuel@sholland.org> | 2023-10-31 00:35:41 -0500 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-11-02 15:15:46 +0800 |
| commit | 3b00fab616b1150da745bbb36f6644842a24624f (patch) | |
| tree | ec370646297026107f4d3d5865648546945e7e05 /arch/riscv/lib/cache.c | |
| parent | a6a77e47343d0b511136b76da0c853304a3f1423 (diff) | |
riscv: Align the trap handler to 64 bytes
This is required on CPUs which always operate in CLIC mode, such as the
T-HEAD E906 and E907. Per the CLIC specification: "In this mode, the
trap vector base address held in mtvec is constrained to be aligned on a
64-byte or larger power-of-two boundary."
Reported-by: Madushan Nishantha <jlmadushan@gmail.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'arch/riscv/lib/cache.c')
0 files changed, 0 insertions, 0 deletions