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| author | Tom Rini <trini@konsulko.com> | 2019-01-15 22:05:05 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-01-15 22:05:05 -0500 |
| commit | 0cd35f392000fb0783149d9b5f66c5f2e01bcbf1 (patch) | |
| tree | b2bc80bd79b2ba7aa387abc575630b03b7470c36 /arch/riscv/lib/cache.c | |
| parent | e807f6b5f9a164dc1fc35e1c733fa343acf335c0 (diff) | |
| parent | 91882c472d8c0aef4db699d3f2de55bf43d4ae4b (diff) | |
Merge git://git.denx.de/u-boot-riscv
1. Improve cache implementation.
2. Fix and improve standalone applications
Diffstat (limited to 'arch/riscv/lib/cache.c')
| -rw-r--r-- | arch/riscv/lib/cache.c | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index ae5c60716f..5437a122a1 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -11,13 +11,12 @@ void invalidate_icache_all(void) asm volatile ("fence.i" ::: "memory"); } -void flush_dcache_all(void) +__weak void flush_dcache_all(void) { - asm volatile ("fence" :::"memory"); } -void flush_dcache_range(unsigned long start, unsigned long end) + +__weak void flush_dcache_range(unsigned long start, unsigned long end) { - flush_dcache_all(); } void invalidate_icache_range(unsigned long start, unsigned long end) @@ -29,9 +28,8 @@ void invalidate_icache_range(unsigned long start, unsigned long end) invalidate_icache_all(); } -void invalidate_dcache_range(unsigned long start, unsigned long end) +__weak void invalidate_dcache_range(unsigned long start, unsigned long end) { - flush_dcache_all(); } void cache_flush(void) @@ -42,8 +40,8 @@ void cache_flush(void) void flush_cache(unsigned long addr, unsigned long size) { - invalidate_icache_all(); - flush_dcache_all(); + invalidate_icache_range(addr, addr + size); + flush_dcache_range(addr, addr + size); } __weak void icache_enable(void) |