diff options
| author | Green Wan <green.wan@sifive.com> | 2021-05-27 06:52:07 -0700 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2021-05-31 16:35:53 +0800 |
| commit | a74e9d899d98037c75ca770d02367e26c179b45c (patch) | |
| tree | 942066f839c98c68e8c41383ac5e405ea93b95c2 /arch/riscv/include/asm/arch-fu740/cache.h | |
| parent | ffd810487ec2ff6095edf3f3d058d7ed6eb85ff3 (diff) | |
riscv: cpu: fu740: Add support for cpu fu740
Add SiFive fu740 cpu to support RISC-V arch
Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/riscv/include/asm/arch-fu740/cache.h')
| -rw-r--r-- | arch/riscv/include/asm/arch-fu740/cache.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/arch-fu740/cache.h b/arch/riscv/include/asm/arch-fu740/cache.h new file mode 100644 index 0000000000..7d4fe9942b --- /dev/null +++ b/arch/riscv/include/asm/arch-fu740/cache.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020-2021 SiFive, Inc. + * + * Authors: + * Pragnesh Patel <pragnesh.patel@sifve.com> + */ + +#ifndef _CACHE_SIFIVE_H +#define _CACHE_SIFIVE_H + +int cache_enable_ways(void); + +#endif /* _CACHE_SIFIVE_H */ |