Merge branch '2023-10-24-assorted-general-fixes-and-updates'

- Remove common.h in a number of places and make checkpatch.pl complain
  about its use in all cases, allow the mbr command to handle 4 primary
  partitions, fix an issue with the pstore command, fix a problem with
  cli parsing of escape sequences, remove and ignore more files, allow
  for the serial port to be flushed with every print (for debugging),
  and add SCMI power domain support.

12 files changed, 0 insertions, 12 deletions

diff --git a/arch/riscv/cpu/andesv5/cache.c b/arch/riscv/cpu/andesv5/cache.c
index 40d77f671c..269bb27f75 100644
--- a/arch/riscv/cpu/andesv5/cache.c
+++ b/arch/riscv/cpu/andesv5/cache.c
@@ -6,7 +6,6 @@
 
 #include <asm/csr.h>
 #include <asm/asm.h>
-#include <common.h>
 #include <cache.h>
 #include <cpu_func.h>
 #include <dm.h>
diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c
index 06e379bcb1..63bc24cdfc 100644
--- a/arch/riscv/cpu/andesv5/cpu.c
+++ b/arch/riscv/cpu/andesv5/cpu.c
@@ -5,7 +5,6 @@
  */
 
 /* CPU specific code */
-#include <common.h>
 #include <cpu_func.h>
 #include <irq_func.h>
 #include <asm/cache.h>
diff --git a/arch/riscv/cpu/andesv5/spl.c b/arch/riscv/cpu/andesv5/spl.c
index 413849043b..a13dc4095a 100644
--- a/arch/riscv/cpu/andesv5/spl.c
+++ b/arch/riscv/cpu/andesv5/spl.c
@@ -3,7 +3,6 @@
  * Copyright (C) 2023 Andes Technology Corporation
  * Rick Chen, Andes Technology Corporation <rick@andestech.com>
  */
-#include <common.h>
 #include <cpu_func.h>
 #include <hang.h>
 #include <init.h>
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index c1a9638c1a..ebd39cb41a 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -3,7 +3,6 @@
  * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
  */
 
-#include <common.h>
 #include <cpu.h>
 #include <dm.h>
 #include <dm/lists.h>
diff --git a/arch/riscv/cpu/fu540/dram.c b/arch/riscv/cpu/fu540/dram.c
index 94d8018407..7b5a3471ac 100644
--- a/arch/riscv/cpu/fu540/dram.c
+++ b/arch/riscv/cpu/fu540/dram.c
@@ -3,7 +3,6 @@
  * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
  */
 
-#include <common.h>
 #include <fdtdec.h>
 #include <init.h>
 #include <asm/global_data.h>
diff --git a/arch/riscv/cpu/fu740/dram.c b/arch/riscv/cpu/fu740/dram.c
index 8657fcd165..61f551763f 100644
--- a/arch/riscv/cpu/fu740/dram.c
+++ b/arch/riscv/cpu/fu740/dram.c
@@ -3,7 +3,6 @@
  * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
  */
 
-#include <common.h>
 #include <fdtdec.h>
 #include <init.h>
 #include <linux/sizes.h>
diff --git a/arch/riscv/cpu/generic/cpu.c b/arch/riscv/cpu/generic/cpu.c
index d78e1a3453..f13c18942f 100644
--- a/arch/riscv/cpu/generic/cpu.c
+++ b/arch/riscv/cpu/generic/cpu.c
@@ -3,7 +3,6 @@
  * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
  */
 
-#include <common.h>
 #include <irq_func.h>
 #include <asm/cache.h>
 
diff --git a/arch/riscv/cpu/generic/dram.c b/arch/riscv/cpu/generic/dram.c
index 1b51bae9b6..91007c0a3d 100644
--- a/arch/riscv/cpu/generic/dram.c
+++ b/arch/riscv/cpu/generic/dram.c
@@ -3,7 +3,6 @@
  * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
  */
 
-#include <common.h>
 #include <fdtdec.h>
 #include <init.h>
 #include <asm/global_data.h>
diff --git a/arch/riscv/cpu/jh7110/dram.c b/arch/riscv/cpu/jh7110/dram.c
index 1a9fa46d14..664b9b93eb 100644
--- a/arch/riscv/cpu/jh7110/dram.c
+++ b/arch/riscv/cpu/jh7110/dram.c
@@ -4,7 +4,6 @@
  * Author: Yanhong Wang <yanhong.wang@starfivetech.com>
  */
 
-#include <common.h>
 #include <fdtdec.h>
 #include <init.h>
 #include <linux/sizes.h>
diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c
index 4047b10efe..6bdf8b9c72 100644
--- a/arch/riscv/cpu/jh7110/spl.c
+++ b/arch/riscv/cpu/jh7110/spl.c
@@ -3,7 +3,6 @@
  * Copyright (C) 2022 StarFive Technology Co., Ltd.
  * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
  */
-#include <common.h>
 #include <asm/arch/eeprom.h>
 #include <asm/csr.h>
 #include <asm/sections.h>
diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S
index e40c7bd3f4..6eb3ed1d5a 100644
--- a/arch/riscv/cpu/mtrap.S
+++ b/arch/riscv/cpu/mtrap.S
@@ -11,7 +11,6 @@
  * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
  */
 
-#include <common.h>
 #include <asm/encoding.h>
 
 #ifdef CONFIG_32BIT
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 30cf674370..6cecadfac5 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -11,7 +11,6 @@
 
 #include <asm-offsets.h>
 #include <config.h>
-#include <common.h>
 #include <elf.h>
 #include <system-constants.h>
 #include <asm/encoding.h>