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authorGreen Wan <green.wan@sifive.com>2021-05-27 06:52:07 -0700
committerLeo Yu-Chi Liang <ycliang@andestech.com>2021-05-31 16:35:53 +0800
commita74e9d899d98037c75ca770d02367e26c179b45c (patch)
tree942066f839c98c68e8c41383ac5e405ea93b95c2 /arch/riscv/cpu/fu740/cpu.c
parentffd810487ec2ff6095edf3f3d058d7ed6eb85ff3 (diff)
riscv: cpu: fu740: Add support for cpu fu740
Add SiFive fu740 cpu to support RISC-V arch Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/riscv/cpu/fu740/cpu.c')
-rw-r--r--arch/riscv/cpu/fu740/cpu.c22
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/riscv/cpu/fu740/cpu.c b/arch/riscv/cpu/fu740/cpu.c
new file mode 100644
index 0000000000..f13c18942f
--- /dev/null
+++ b/arch/riscv/cpu/fu740/cpu.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <irq_func.h>
+#include <asm/cache.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+ disable_interrupts();
+
+ cache_flush();
+
+ return 0;
+}