diff options
| author | Tom Rini <trini@konsulko.com> | 2018-11-26 13:45:29 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-11-26 15:52:39 -0500 |
| commit | ef0b75d3d8afccebd3b9822de6bcae358d4bc0e3 (patch) | |
| tree | 9a1e0c04a8a3ecd641f0e219991eaf6ce98eefed /arch/riscv/cpu/cpu.c | |
| parent | 6b21502229035779059493b2193fd790448fe85e (diff) | |
| parent | 52923c6db7f00e0197ec894c8c1bb8a7681974bb (diff) | |
Merge git://git.denx.de/u-boot-riscv
Diffstat (limited to 'arch/riscv/cpu/cpu.c')
| -rw-r--r-- | arch/riscv/cpu/cpu.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index ae57fb8313..d9f820c44c 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -6,6 +6,12 @@ #include <common.h> #include <asm/csr.h> +/* + * prior_stage_fdt_address must be stored in the data section since it is used + * before the bss section is available. + */ +phys_addr_t prior_stage_fdt_address __attribute__((section(".data"))); + enum { ISA_INVALID = 0, ISA_32BIT, |