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| author | Wolfgang Denk <wd@denx.de> | 2011-02-06 22:28:34 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2011-02-06 22:28:34 +0100 |
| commit | e9e481f74b4ebb75858a535a79dbb1cde6aff0b6 (patch) | |
| tree | 9eb9f92fd053600c37f77d36ea86f53ce23acfb1 /arch/powerpc/include | |
| parent | f69b980d108b5f15ca7dd3f4284d5a66488c3625 (diff) | |
| parent | 04a641df25c73283ce22dc5fdf8bc6d56d1d3742 (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'arch/powerpc/include')
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 6 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/fsl_ddr_sdram.h | 5 |
2 files changed, 11 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 36464aa7cc..3a29d1cd2f 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -77,6 +77,8 @@ #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_DDR_115 +#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 #elif defined(CONFIG_P1010) #define CONFIG_MAX_CPUS 1 @@ -130,11 +132,15 @@ #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 #elif defined(CONFIG_P2020) #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_SEC_COMPAT 2 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 #elif defined(CONFIG_PPC_P2040) #define CONFIG_MAX_CPUS 4 diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index 852e5c3bd0..02a1f5d323 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -89,6 +89,11 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #define SDRAM_CFG_2T_EN 0x00008000 #define SDRAM_CFG_BI 0x00000001 +#define SDRAM_CFG2_D_INIT 0x00000010 +#define SDRAM_CFG2_ODT_CFG_MASK 0x00600000 + +#define TIMING_CFG_2_CPO_MASK 0x0F800000 + #if defined(CONFIG_P4080) #define RD_TO_PRE_MASK 0xf #define RD_TO_PRE_SHIFT 13 |