Merge branch '2021-04-11-remove-non-migrated-boards'

- Remove a large number of boards that have not migrated to DM_MMC, for
  which the migration deadline with 2 years ago at v2019.04.

3 files changed, 5 insertions, 45 deletions

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 4d70259f09..2053548731 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -66,10 +66,6 @@
 #define QE_NUM_OF_SNUM			28
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 
-#elif defined(CONFIG_ARCH_P1022)
-#define CONFIG_TSECV2
-#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
-
 #elif defined(CONFIG_ARCH_P1023)
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_NUM_FM1_DTSEC	2
@@ -157,24 +153,6 @@
 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
 
-#elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */
-#define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
-#define CONFIG_SYS_FSL_NUM_CC_PLLS	2
-#define CONFIG_SYS_NUM_FMAN		1
-#define CONFIG_SYS_NUM_FM1_DTSEC	5
-#define CONFIG_SYS_NUM_FM1_10GEC	1
-#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
-#define CONFIG_SYS_FM_MURAM_SIZE	0x28000
-#define CONFIG_SYS_FSL_TBCLK_DIV	32
-#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
-#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
-#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
-#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
-
 #elif defined(CONFIG_ARCH_P5040)
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	3
@@ -364,7 +342,7 @@
 #define QE_NUM_OF_SNUM			28
 #define CONFIG_SYS_FSL_SFP_VER_3_0
 
-#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
+#elif defined(CONFIG_ARCH_T2080)
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
@@ -381,9 +359,6 @@
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
-#elif defined(CONFIG_ARCH_T2081)
-#define CONFIG_SYS_NUM_FM1_DTSEC	6
-#define CONFIG_SYS_NUM_FM1_10GEC	2
 #endif
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
 #define CONFIG_PME_PLAT_CLK_DIV		1
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index 035bf12467..6499e10ef4 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -25,7 +25,6 @@
 	defined(CONFIG_TARGET_T4240QDS) || \
 	defined(CONFIG_TARGET_T2080QDS) || \
 	defined(CONFIG_TARGET_T2080RDB) || \
-	defined(CONFIG_TARGET_T1040QDS) || \
 	defined(CONFIG_TARGET_T1040RDB) || \
 	defined(CONFIG_TARGET_T1040D4RDB) || \
 	defined(CONFIG_TARGET_T1042RDB) || \
@@ -58,7 +57,6 @@
 
 #if defined(CONFIG_ARCH_P3041)	||	\
 	defined(CONFIG_ARCH_P4080) ||	\
-	defined(CONFIG_ARCH_P5020) ||	\
 	defined(CONFIG_ARCH_P5040) ||	\
 	defined(CONFIG_ARCH_P2041)
 	#define	CONFIG_FSL_TRUST_ARCH_v1
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 905613fa31..59bc32fd17 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1808,7 +1808,7 @@ typedef struct ccsr_gur {
 #define PXCKEN_MASK				0x80000000
 #define PXCK_MASK				0x00FF0000
 #define PXCK_BITS_START				16
-#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
+#elif defined(CONFIG_ARCH_T2080)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL		0xff000000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	24
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL		0x00ff0000
@@ -1853,7 +1853,7 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_RCWSR11_EC2_USB2			0x00100000
 #endif
 #if defined(CONFIG_ARCH_P2041) || \
-	defined(CONFIG_ARCH_P3041) || defined(CONFIG_ARCH_P5020)
+	defined(CONFIG_ARCH_P3041)
 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII	0x00000000
 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII		0x00800000
 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE		0x00c00000
@@ -1880,7 +1880,7 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII	0x08000000
 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO		0x10000000
 #endif
-#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
+#if defined(CONFIG_ARCH_T2080)
 #define FSL_CORENET_RCWSR13_EC1			0x60000000 /* bits 417..418 */
 #define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII	0x00000000
 #define FSL_CORENET_RCWSR13_EC1_GPIO		0x40000000
@@ -2157,10 +2157,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PORDEVSR_SGMII4_DIS	0x04000000
 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL	0x38000000
 #define MPC85xx_PORDEVSR_PCI1		0x00800000
-#if defined(CONFIG_ARCH_P1022)
-#define MPC85xx_PORDEVSR_IO_SEL		0x007c0000
-#define MPC85xx_PORDEVSR_IO_SEL_SHIFT	18
-#elif defined(CONFIG_ARCH_P1023)
+#if defined(CONFIG_ARCH_P1023)
 #define MPC85xx_PORDEVSR_IO_SEL		0x00600000
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT	21
 #else
@@ -2278,12 +2275,6 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR_QE11		0x00000010
 #define MPC85xx_PMUXCR_QE12		0x00000008
 #endif
-#if defined(CONFIG_ARCH_P1022)
-#define MPC85xx_PMUXCR_TDM_MASK		0x0001cc00
-#define MPC85xx_PMUXCR_TDM		0x00014800
-#define MPC85xx_PMUXCR_SPI_MASK		0x00600000
-#define MPC85xx_PMUXCR_SPI		0x00000000
-#endif
 #if defined(CONFIG_ARCH_BSC9131)
 #define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ	0x40000000
 #define MPC85xx_PMUXCR_TSEC2_USB		0xC0000000
@@ -2363,10 +2354,6 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY	0x00002000
 #define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE		0x00001000
 #endif
-#if defined(CONFIG_ARCH_P1022)
-#define MPC85xx_PMUXCR2_ETSECUSB_MASK	0x001f8000
-#define MPC85xx_PMUXCR2_USB		0x00150000
-#endif
 #if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
 #if defined(CONFIG_ARCH_BSC9131)
 #define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD		0X40000000