diff options
| author | Tom Rini <trini@ti.com> | 2013-08-13 09:14:02 -0400 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-08-13 09:14:02 -0400 |
| commit | b98d934128bcd98106e764d2f492ac79c38ae53d (patch) | |
| tree | 5e078614fccb51f34fa8f7aa8d92c4f5f518b686 /arch/powerpc/cpu/mpc85xx/cpu.c | |
| parent | 67cafc0861477bf19a587508ed13f4538c7a281e (diff) | |
| parent | 3aab0cd852d7c9565c2559a7983cbb73852bac28 (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/cpu.c')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu.c | 23 |
1 files changed, 19 insertions, 4 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 91ac4ee617..66bc6a2ea3 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -44,10 +44,10 @@ int checkcpu (void) uint major, minor; struct cpu_type *cpu; char buf1[32], buf2[32]; -#if (defined(CONFIG_DDR_CLK_FREQ) || \ - defined(CONFIG_FSL_CORENET)) && !defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); -#endif /* CONFIG_FSL_CORENET */ +#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) + ccsr_gur_t __iomem *gur = + (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif /* * Cornet platforms use ddr sync bit in RCW to indicate sync vs async @@ -211,6 +211,21 @@ int checkcpu (void) puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); +#ifdef CONFIG_FSL_CORENET + /* Display the RCW, so that no one gets confused as to what RCW + * we're actually using for this boot. + */ + puts("Reset Configuration Word (RCW):"); + for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { + u32 rcw = in_be32(&gur->rcwsr[i]); + + if ((i % 4) == 0) + printf("\n %08x:", i * 4); + printf(" %08x", rcw); + } + puts("\n"); +#endif + return 0; } |