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| author | Stefano Babic <sbabic@denx.de> | 2015-10-30 14:52:51 +0100 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2015-10-30 14:52:51 +0100 |
| commit | e573bdb324c78fac56655a493bea843842c9d9f8 (patch) | |
| tree | 3933d354a6be71cbe66d583fec3f5b2479e596ee /arch/nios2/include/asm/cache.h | |
| parent | a69fdc7787bfa2f27eed74c2ee58c28ce932d502 (diff) | |
| parent | 0eb4cf9c14315e1976a116de75da6f420ac0e8dd (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot
Diffstat (limited to 'arch/nios2/include/asm/cache.h')
| -rw-r--r-- | arch/nios2/include/asm/cache.h | 13 |
1 files changed, 3 insertions, 10 deletions
diff --git a/arch/nios2/include/asm/cache.h b/arch/nios2/include/asm/cache.h index 9b87c9f755..dde43cd6fc 100644 --- a/arch/nios2/include/asm/cache.h +++ b/arch/nios2/include/asm/cache.h @@ -8,18 +8,11 @@ #ifndef __ASM_NIOS2_CACHE_H_ #define __ASM_NIOS2_CACHE_H_ -extern void flush_dcache (unsigned long start, unsigned long size); -extern void flush_icache (unsigned long start, unsigned long size); - /* - * Valid L1 data cache line sizes for the NIOS2 architecture are 4, 16, and 32 - * bytes. If the board configuration has not specified one we default to the - * largest of these values for alignment of DMA buffers. + * Valid L1 data cache line sizes for the NIOS2 architecture are 4, + * 16, and 32 bytes. We default to the largest of these values for + * alignment of DMA buffers. */ -#ifdef CONFIG_SYS_CACHELINE_SIZE -#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE -#else #define ARCH_DMA_MINALIGN 32 -#endif #endif /* __ASM_NIOS2_CACHE_H_ */ |