Merge tag 'mips-updates-for-2019.11' of git://git.denx.de/u-boot-mips

- mips: fix some DTC warnings
- bmips: bcm6348: add DMA driver
- bmips: bcm5348: add ethernet driver
- bmips: bcm6368: add ethernet driver
- mips: mt76xx: fix DMA problems, disable CONFIG_OF_EMBED
- mips: mscc: add support for Microsemi Ocelot and Luton SoCs
- mips: mscc: add support for Ocelot and Luton evaluation boards
- mips: jz47xx: add basic support for Ingenic JZ4780 SoC
- mips: jz47xx: add support for Imgtec Creator CI20 board

1 files changed, 30 insertions, 0 deletions

diff --git a/arch/mips/mach-mscc/reset.c b/arch/mips/mach-mscc/reset.c
new file mode 100644
index 0000000000..390bbd086a
--- /dev/null
+++ b/arch/mips/mach-mscc/reset.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+
+#include <asm/sections.h>
+#include <asm/io.h>
+
+#include <asm/reboot.h>
+
+void _machine_restart(void)
+{
+	register u32 resetbits = PERF_SOFT_RST_SOFT_CHIP_RST;
+	(void)readl(BASE_DEVCPU_GCB + PERF_SOFT_RST);
+
+	/* Make sure VCore is NOT protected from reset */
+	clrbits_le32(BASE_CFG + ICPU_RESET, ICPU_RESET_CORE_RST_PROTECT);
+
+	/* Change to SPI bitbang for SPI reset workaround... */
+	writel(ICPU_SW_MODE_SW_SPI_CS_OE(1) | ICPU_SW_MODE_SW_SPI_CS(1) |
+	       ICPU_SW_MODE_SW_PIN_CTRL_MODE, BASE_CFG + ICPU_SW_MODE);
+
+	/* Do the global reset */
+	writel(resetbits, BASE_DEVCPU_GCB + PERF_SOFT_RST);
+
+	while (1)
+		; /* NOP */
+}