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| author | Tom Rini <trini@konsulko.com> | 2020-04-09 19:23:48 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-04-09 19:23:48 -0400 |
| commit | a7ae587f9325aa072617dae109d474f623b38a3e (patch) | |
| tree | df5fa02d7a67a07c6e833f9175998045391ac813 /arch/mips/mach-mscc/lowlevel_init.S | |
| parent | 31232de07ef2bd97ff67625976eecd97eeb1bd3d (diff) | |
| parent | fb9acad30562177287d8cffec19e5dfa6f072de7 (diff) | |
Merge tag 'mips-fixes-for-2020.04' of git://git.denx.de/u-boot-mips
- doc: fix code examples in qemu-mips.rst
- mips: vcoreiii: fix memtest and cache coherency issues
- cmd/go: fix cache coherency issues on MIPS
Diffstat (limited to 'arch/mips/mach-mscc/lowlevel_init.S')
| -rw-r--r-- | arch/mips/mach-mscc/lowlevel_init.S | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/arch/mips/mach-mscc/lowlevel_init.S b/arch/mips/mach-mscc/lowlevel_init.S index dfbe06766c..91f29ae252 100644 --- a/arch/mips/mach-mscc/lowlevel_init.S +++ b/arch/mips/mach-mscc/lowlevel_init.S @@ -8,6 +8,7 @@ .set noreorder .extern vcoreiii_tlb_init + .extern vcoreiii_ddr_init #ifdef CONFIG_SOC_LUTON .extern pll_init #endif @@ -17,14 +18,28 @@ LEAF(lowlevel_init) * As we have no stack yet, we can assume the restricted * luxury of the sX-registers without saving them */ - move s0,ra + + /* Modify ra/s0 such we return to physical NOR location */ + li t0, 0x0fffffff + li t1, CONFIG_SYS_TEXT_BASE + and s0, ra, t0 + add s0, s0, t1 jal vcoreiii_tlb_init nop + #ifdef CONFIG_SOC_LUTON jal pll_init nop #endif + + /* Initialize DDR controller to enable stack/gd/heap */ +0: + jal vcoreiii_ddr_init + nop + bnez v0, 0b /* Retry on error */ + nop + jr s0 nop END(lowlevel_init) |