diff options
| author | Tom Rini <trini@konsulko.com> | 2020-04-09 19:23:48 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-04-09 19:23:48 -0400 |
| commit | a7ae587f9325aa072617dae109d474f623b38a3e (patch) | |
| tree | df5fa02d7a67a07c6e833f9175998045391ac813 /arch/mips/mach-mscc/include/mach/ddr.h | |
| parent | 31232de07ef2bd97ff67625976eecd97eeb1bd3d (diff) | |
| parent | fb9acad30562177287d8cffec19e5dfa6f072de7 (diff) | |
Merge tag 'mips-fixes-for-2020.04' of git://git.denx.de/u-boot-mips
- doc: fix code examples in qemu-mips.rst
- mips: vcoreiii: fix memtest and cache coherency issues
- cmd/go: fix cache coherency issues on MIPS
Diffstat (limited to 'arch/mips/mach-mscc/include/mach/ddr.h')
| -rw-r--r-- | arch/mips/mach-mscc/include/mach/ddr.h | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/mips/mach-mscc/include/mach/ddr.h b/arch/mips/mach-mscc/include/mach/ddr.h index d1f4287f65..bf75e52ec3 100644 --- a/arch/mips/mach-mscc/include/mach/ddr.h +++ b/arch/mips/mach-mscc/include/mach/ddr.h @@ -435,16 +435,12 @@ static inline void hal_vcoreiii_ddr_failed(void) reset = KSEG0ADDR(_machine_restart); icache_lock((void *)reset, 128); asm volatile ("jr %0"::"r" (reset)); - - panic("DDR init failed\n"); } #else /* JR2 || ServalT */ static inline void hal_vcoreiii_ddr_failed(void) { writel(0, BASE_CFG + ICPU_RESET); writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_CFG + PERF_SOFT_RST); - - panic("DDR init failed\n"); } #endif |