diff options
author | Tom Rini <trini@konsulko.com> | 2020-04-09 19:23:48 -0400 |
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committer | Tom Rini <trini@konsulko.com> | 2020-04-09 19:23:48 -0400 |
commit | a7ae587f9325aa072617dae109d474f623b38a3e (patch) | |
tree | df5fa02d7a67a07c6e833f9175998045391ac813 /arch/mips/mach-mscc/cpu.c | |
parent | 31232de07ef2bd97ff67625976eecd97eeb1bd3d (diff) | |
parent | fb9acad30562177287d8cffec19e5dfa6f072de7 (diff) |
Merge tag 'mips-fixes-for-2020.04' of git://git.denx.de/u-boot-mips
- doc: fix code examples in qemu-mips.rst
- mips: vcoreiii: fix memtest and cache coherency issues
- cmd/go: fix cache coherency issues on MIPS
Diffstat (limited to 'arch/mips/mach-mscc/cpu.c')
-rw-r--r-- | arch/mips/mach-mscc/cpu.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/arch/mips/mach-mscc/cpu.c b/arch/mips/mach-mscc/cpu.c index ac75d51da5..3ee589891b 100644 --- a/arch/mips/mach-mscc/cpu.c +++ b/arch/mips/mach-mscc/cpu.c @@ -7,6 +7,7 @@ #include <asm/io.h> #include <asm/types.h> +#include <asm/mipsregs.h> #include <mach/tlb.h> #include <mach/ddr.h> @@ -53,7 +54,6 @@ void vcoreiii_tlb_init(void) MMU_REGIO_RW); #endif -#if CONFIG_SYS_TEXT_BASE == MSCC_FLASH_TO /* * If U-Boot is located in NOR then we want to be able to use * the data cache in order to boot in a decent duration @@ -71,9 +71,10 @@ void vcoreiii_tlb_init(void) create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW, MSCC_ATTRIB2); - /* Enable caches by clearing the bit ERL, which is set on reset */ - write_c0_status(read_c0_status() & ~BIT(2)); -#endif /* CONFIG_SYS_TEXT_BASE */ + /* Enable mapping (using TLB) kuseg by clearing the bit ERL, + * which is set on reset. + */ + write_c0_status(read_c0_status() & ~ST0_ERL); } int mach_cpu_init(void) |