diff options
author | Tom Rini <trini@konsulko.com> | 2018-12-21 13:36:51 -0500 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2018-12-21 13:36:51 -0500 |
commit | fd0135e3c54c391b6143f85440e30d576a9a83fe (patch) | |
tree | 500ea3c4490f65e30c20e73e571f7982cd6f8c82 /arch/mips/mach-jz47xx/jz4780/gpio.c | |
parent | 328e3f8a706931e1a8f76adfdc015ad76cbeb83c (diff) | |
parent | 25c7de2255128743fcbe436b6f3b17a70d0cdd82 (diff) |
Merge tag 'mips-updates-for-2019.11' of git://git.denx.de/u-boot-mips
- mips: fix some DTC warnings
- bmips: bcm6348: add DMA driver
- bmips: bcm5348: add ethernet driver
- bmips: bcm6368: add ethernet driver
- mips: mt76xx: fix DMA problems, disable CONFIG_OF_EMBED
- mips: mscc: add support for Microsemi Ocelot and Luton SoCs
- mips: mscc: add support for Ocelot and Luton evaluation boards
- mips: jz47xx: add basic support for Ingenic JZ4780 SoC
- mips: jz47xx: add support for Imgtec Creator CI20 board
Diffstat (limited to 'arch/mips/mach-jz47xx/jz4780/gpio.c')
-rw-r--r-- | arch/mips/mach-jz47xx/jz4780/gpio.c | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/arch/mips/mach-jz47xx/jz4780/gpio.c b/arch/mips/mach-jz47xx/jz4780/gpio.c new file mode 100644 index 0000000000..cee2328ab1 --- /dev/null +++ b/arch/mips/mach-jz47xx/jz4780/gpio.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <mach/jz4780.h> + +int jz47xx_gpio_get_value(unsigned int gpio) +{ + void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; + int port = gpio / 32; + int pin = gpio % 32; + + return readl(gpio_regs + GPIO_PXPIN(port)) & BIT(pin); +} + +void jz47xx_gpio_direction_input(unsigned int gpio) +{ + void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; + int port = gpio / 32; + int pin = gpio % 32; + + writel(BIT(pin), gpio_regs + GPIO_PXINTC(port)); + writel(BIT(pin), gpio_regs + GPIO_PXMASKS(port)); + writel(BIT(pin), gpio_regs + GPIO_PXPAT1S(port)); +} + +void jz47xx_gpio_direction_output(unsigned int gpio, int value) +{ + void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; + int port = gpio / 32; + int pin = gpio % 32; + + writel(BIT(pin), gpio_regs + GPIO_PXINTC(port)); + writel(BIT(pin), gpio_regs + GPIO_PXMASKS(port)); + writel(BIT(pin), gpio_regs + GPIO_PXPAT1C(port)); + writel(BIT(pin), gpio_regs + + (value ? GPIO_PXPAT0S(port) : GPIO_PXPAT0C(port))); +} |