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| author | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2016-01-12 21:48:26 +0100 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2016-01-16 21:06:46 +0100 |
| commit | a3ab2ae7f6c8724152f05144946a76b727fb1c7e (patch) | |
| tree | c779e8946259fc769f3ada4ec6f6880b953e3162 /arch/mips/lib/cache_init.S | |
| parent | 23ff8633fd8ca75d2ffd4595b9c72bb1a5fdbd20 (diff) | |
MIPS: sync processor and register definitions with linux-4.4
Update definitions for processor, registers as well as assemby
macros.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Diffstat (limited to 'arch/mips/lib/cache_init.S')
| -rw-r--r-- | arch/mips/lib/cache_init.S | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S index 137d7283ff..14cc2c49fd 100644 --- a/arch/mips/lib/cache_init.S +++ b/arch/mips/lib/cache_init.S @@ -54,24 +54,24 @@ mfc0 $1, CP0_CONFIG, 1 /* detect line size */ - srl \line_sz, $1, \off + MIPS_CONF1_DL_SHIFT - MIPS_CONF1_DA_SHIFT - andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHIFT) + srl \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF + andi \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF) move \sz, zero beqz \line_sz, 10f li \sz, 2 sllv \line_sz, \sz, \line_sz /* detect associativity */ - srl \sz, $1, \off + MIPS_CONF1_DA_SHIFT - MIPS_CONF1_DA_SHIFT - andi \sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHIFT) + srl \sz, $1, \off + MIPS_CONF1_DA_SHF - MIPS_CONF1_DA_SHF + andi \sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHF) addi \sz, \sz, 1 /* sz *= line_sz */ mul \sz, \sz, \line_sz /* detect log32(sets) */ - srl $1, $1, \off + MIPS_CONF1_DS_SHIFT - MIPS_CONF1_DA_SHIFT - andi $1, $1, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHIFT) + srl $1, $1, \off + MIPS_CONF1_DS_SHF - MIPS_CONF1_DA_SHF + andi $1, $1, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHF) addiu $1, $1, 1 andi $1, $1, 0x7 @@ -103,14 +103,14 @@ LEAF(mips_cache_reset) li t2, CONFIG_SYS_ICACHE_SIZE li t8, CONFIG_SYS_CACHELINE_SIZE #else - l1_info t2, t8, MIPS_CONF1_IA_SHIFT + l1_info t2, t8, MIPS_CONF1_IA_SHF #endif #ifdef CONFIG_SYS_DCACHE_SIZE li t3, CONFIG_SYS_DCACHE_SIZE li t9, CONFIG_SYS_CACHELINE_SIZE #else - l1_info t3, t9, MIPS_CONF1_DA_SHIFT + l1_info t3, t9, MIPS_CONF1_DA_SHF #endif #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD |