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| author | Tom Rini <trini@ti.com> | 2015-01-30 13:56:15 -0500 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2015-01-30 13:56:15 -0500 |
| commit | a0573d19885236ba03d412f7788104f75f0dea64 (patch) | |
| tree | 95432f4b7dba3fb9fd4a7d8a4fc61330c7d8c734 /arch/mips/include/asm/cacheops.h | |
| parent | 8e3da9dd113699eed2fa05fcde3c55a2ff410913 (diff) | |
| parent | eef88dfb3e16e4631e078f42714dbcef3216e3e1 (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-mips
Diffstat (limited to 'arch/mips/include/asm/cacheops.h')
| -rw-r--r-- | arch/mips/include/asm/cacheops.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h index 6464250d84..75ec380980 100644 --- a/arch/mips/include/asm/cacheops.h +++ b/arch/mips/include/asm/cacheops.h @@ -11,6 +11,19 @@ #ifndef __ASM_CACHEOPS_H #define __ASM_CACHEOPS_H +#ifndef __ASSEMBLY__ + +static inline void mips_cache(int op, const volatile void *addr) +{ +#ifdef __GCC_HAVE_BUILTIN_MIPS_CACHE + __builtin_mips_cache(op, addr); +#else + __asm__ __volatile__("cache %0, %1" : : "i"(op), "R"(addr)) +#endif +} + +#endif /* !__ASSEMBLY__ */ + /* * Cache Operations available on all MIPS processors with R4000-style caches */ |