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authorTom Rini <trini@konsulko.com>2021-08-26 11:47:59 -0400
committerTom Rini <trini@konsulko.com>2021-08-31 17:47:49 -0400
commitab92b38a0161f0d8efa1c2112d944ef8f755dfbe (patch)
treef4413fb22813b940ce12ca5079c67c7149ade8e3 /arch/mips/include/asm/cache.h
parente4ddf14305b28e788e09a9b1b5b2b2474234eb91 (diff)
Finish converting CONFIG_SYS_CACHELINE_SIZE to Kconfig
We move the SYS_CACHE_SHIFT_N options from arch/arm/Kconfig to arch/Kconfig, and introduce SYS_CACHE_SHIFT_4 to provide a size of 16. Introduce select statements for other architectures based on current usage. For MIPS, we take the existing arch-specific symbol and migrate to the generic symbol. This lets us remove a little bit of otherwise unused code. Cc: Alexey Brodkin <alexey.brodkin@synopsys.com> Cc: Anup Patel <anup.patel@wdc.com> Cc: Atish Patra <atish.patra@wdc.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Leo <ycliang@andestech.com> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Sean Anderson <seanga2@gmail.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'arch/mips/include/asm/cache.h')
-rw-r--r--arch/mips/include/asm/cache.h12
1 files changed, 1 insertions, 11 deletions
diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h
index 00696e672d..d3e8a8cd41 100644
--- a/arch/mips/include/asm/cache.h
+++ b/arch/mips/include/asm/cache.h
@@ -6,17 +6,7 @@
#ifndef __MIPS_CACHE_H__
#define __MIPS_CACHE_H__
-#define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT
-#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
-
-#define ARCH_DMA_MINALIGN (L1_CACHE_BYTES)
-
-/*
- * CONFIG_SYS_CACHELINE_SIZE is still used in various drivers primarily for
- * DMA buffer alignment. Satisfy those drivers by providing it as a synonym
- * of ARCH_DMA_MINALIGN for now.
- */
-#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
+#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
#ifndef __ASSEMBLY__
/**