global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace

Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

36 files changed, 259 insertions, 259 deletions

diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c b/arch/arm/cpu/armv7/ls102xa/clock.c
index 86b5b21ef8..4e1fe28120 100644
--- a/arch/arm/cpu/armv7/ls102xa/clock.c
+++ b/arch/arm/cpu/armv7/ls102xa/clock.c
@@ -15,8 +15,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 void get_sys_info(struct sys_info *sys_info)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-	struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_LS1_CLK_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_clk *clk = (void *)(CFG_SYS_FSL_LS1_CLK_ADDR);
 	unsigned int cpu;
 	const u8 core_cplx_pll[6] = {
 		[0] = 0,	/* CC1 PPL / 1 */
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index 0b3e3b2064..d530e0655b 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -228,7 +228,7 @@ void enable_caches(void)
 
 uint get_svr(void)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 
 	return in_be32(&gur->svr);
 }
@@ -237,7 +237,7 @@ uint get_svr(void)
 int print_cpuinfo(void)
 {
 	char buf1[32], buf2[32];
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 	unsigned int svr, major, minor, ver, i;
 
 	svr = in_be32(&gur->svr);
@@ -316,7 +316,7 @@ int arch_cpu_init(void)
 	void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
 	void *rcpm2_base =
 		(void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
-	struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+	struct ccsr_scfg *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
 	u32 state;
 
 	icache_enable();
@@ -355,7 +355,7 @@ int arch_cpu_init(void)
 /* Set the address at which the secondary core starts from.*/
 void smp_set_core_boot_addr(unsigned long addr, int corenr)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 
 	out_be32(&gur->scratchrw[0], addr);
 }
@@ -363,7 +363,7 @@ void smp_set_core_boot_addr(unsigned long addr, int corenr)
 /* Release the secondary core from holdoff state and kick it */
 void smp_kick_all_cpus(void)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 
 	out_be32(&gur->brrl, 0x2);
 
diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c
index 83f9882d0b..c01cebbf98 100644
--- a/arch/arm/cpu/armv7/ls102xa/fdt.c
+++ b/arch/arm/cpu/armv7/ls102xa/fdt.c
@@ -92,7 +92,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 	int off;
 	int val;
 	const char *sysclk_path;
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 	unsigned int svr;
 	svr = in_be32(&gur->svr);
 
@@ -105,7 +105,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 	else {
 		ccsr_sec_t __iomem *sec;
 
-		sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+		sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
 		fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
 	}
 #endif
diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
index caf51e17b3..f74d819ea1 100644
--- a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
+++ b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
@@ -39,7 +39,7 @@ int is_serdes_configured(enum srds_prtcl device)
 
 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 	u32 cfg = in_be32(&gur->rcwsr[4]);
 	int i;
 
@@ -74,7 +74,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 
 u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 	u64 serdes_prtcl_map = 0;
 	u32 cfg;
 	int lane;
@@ -103,14 +103,14 @@ void fsl_serdes_init(void)
 #ifdef CONFIG_SYS_FSL_SRDS_1
 	if (!(serdes1_prtcl_map & (1ULL << NONE)))
 		serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
-					CONFIG_SYS_FSL_SERDES_ADDR,
+					CFG_SYS_FSL_SERDES_ADDR,
 					RCWSR4_SRDS1_PRTCL_MASK,
 					RCWSR4_SRDS1_PRTCL_SHIFT);
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
 	if (!(serdes2_prtcl_map & (1ULL << NONE)))
 		serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
-					CONFIG_SYS_FSL_SERDES_ADDR +
+					CFG_SYS_FSL_SERDES_ADDR +
 					FSL_SRDS_2 * 0x1000,
 					RCWSR4_SRDS2_PRTCL_MASK,
 					RCWSR4_SRDS2_PRTCL_SHIFT);
diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
index 28a7945207..b4d113dc1e 100644
--- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
+++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
@@ -31,7 +31,7 @@ static void __secure ls1_save_ddr_head(void)
 {
 	const char *src = (const char *)CONFIG_SYS_SDRAM_BASE;
 	char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN);
-	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+	struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
 	int i;
 
 	out_le32(&scfg->sparecr[2], dest);
@@ -57,8 +57,8 @@ static void __secure ls1_fsm_setup(void)
 
 static void __secure ls1_deepsleep_irq_cfg(void)
 {
-	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
-	struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
+	struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
+	struct ccsr_rcpm __iomem *rcpm = (void *)CFG_SYS_FSL_RCPM_ADDR;
 	u32 ippdexpcr0, ippdexpcr1, pmcintecr = 0;
 
 	/* Mask interrupts from GIC */
@@ -120,8 +120,8 @@ static void __secure ls1_start_fsm(void)
 {
 	void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
 	void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR;
-	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
-	struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+	struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
+	struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
 
 	/* Set HRSTCR */
 	setbits_be32(&scfg->hrstcr, 0x80000000);
@@ -155,9 +155,9 @@ static void __secure ls1_start_fsm(void)
 
 static void __secure ls1_deep_sleep(u32 entry_point)
 {
-	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
-	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
-	struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
+	struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
+	struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
+	struct ccsr_rcpm __iomem *rcpm = (void *)CFG_SYS_FSL_RCPM_ADDR;
 #ifdef QIXIS_BASE
 	u32 tmp;
 	void *qixis_base = (void *)QIXIS_BASE;
@@ -213,8 +213,8 @@ static void __secure ls1_deep_sleep(u32 entry_point)
 #else
 static void __secure ls1_sleep(void)
 {
-	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
-	struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
+	struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
+	struct ccsr_rcpm __iomem *rcpm = (void *)CFG_SYS_FSL_RCPM_ADDR;
 
 #ifdef QIXIS_BASE
 	u32 tmp;
diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S
index 3956178369..e7c4fbfb43 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -129,8 +129,8 @@ psci_cpu_on:
 	mov	r1, r4
 
 	@ Get DCFG base address
-	movw	r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
-	movt	r4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
+	movw	r4, #(CFG_SYS_FSL_GUTS_ADDR & 0xffff)
+	movt	r4, #(CFG_SYS_FSL_GUTS_ADDR >> 16)
 
 	@ Detect target CPU state
 	ldr	r2, [r4, #DCFG_CCSR_BRR]
@@ -141,8 +141,8 @@ psci_cpu_on:
 
 	@ Reset target CPU
 	@ Get SCFG base address
-	movw	r0, #(CONFIG_SYS_FSL_SCFG_ADDR & 0xffff)
-	movt	r0, #(CONFIG_SYS_FSL_SCFG_ADDR >> 16)
+	movw	r0, #(CFG_SYS_FSL_SCFG_ADDR & 0xffff)
+	movt	r0, #(CFG_SYS_FSL_SCFG_ADDR >> 16)
 
 	@ Enable CORE Soft Reset
 	movw	r5, #0
@@ -216,8 +216,8 @@ psci_affinity_info:
 	mov	r1, r4
 
 	@ Get RCPM base address
-	movw	r4, #(CONFIG_SYS_FSL_RCPM_ADDR & 0xffff)
-	movt	r4, #(CONFIG_SYS_FSL_RCPM_ADDR >> 16)
+	movw	r4, #(CFG_SYS_FSL_RCPM_ADDR & 0xffff)
+	movt	r4, #(CFG_SYS_FSL_RCPM_ADDR >> 16)
 
 	mov	r0, #PSCI_AFFINITY_LEVEL_ON
 
@@ -236,8 +236,8 @@ out_affinity_info:
 .globl	psci_system_reset
 psci_system_reset:
 	@ Get DCFG base address
-	movw	r1, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
-	movt	r1, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
+	movw	r1, #(CFG_SYS_FSL_GUTS_ADDR & 0xffff)
+	movt	r1, #(CFG_SYS_FSL_GUTS_ADDR >> 16)
 
 	mov	r2, #DCFG_CCSR_RSTCR_RESET_REQ
 	rev	r2, r2
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 728efc46f9..1dafa3c1b4 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -54,7 +54,7 @@ struct smmu_stream_id dev_stream_id[] = {
 
 unsigned int get_soc_major_rev(void)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 	unsigned int svr, major;
 
 	svr = in_be32(&gur->svr);
@@ -113,7 +113,7 @@ static void erratum_a008850_early(void)
 	/* part 1 of 2 */
 	struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
 						CONFIG_SYS_CCI400_OFFSET);
-	struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+	struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
 
 	/* disables propagation of barrier transactions to DDRC from CCI400 */
 	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
@@ -129,7 +129,7 @@ void erratum_a008850_post(void)
 	/* part 2 of 2 */
 	struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
 						CONFIG_SYS_CCI400_OFFSET);
-	struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+	struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
 	u32 tmp;
 
 	/* enable propagation of barrier transactions to DDRC from CCI400 */
@@ -161,7 +161,7 @@ void erratum_a010315(void)
 
 int arch_soc_init(void)
 {
-	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
 					CONFIG_SYS_CCI400_OFFSET);
 	unsigned int major;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 487c0ed553..c11341a1d3 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -96,11 +96,11 @@ static struct mm_region early_map[] = {
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+	{ CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
 	  SYS_FSL_OCRAM_SPACE_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 	},
-	{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+	{ CFG_SYS_FSL_QSPI_BASE1, CFG_SYS_FSL_QSPI_BASE1,
 	  CONFIG_SYS_FSL_QSPI_SIZE1,
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
 #ifdef CONFIG_FSL_IFC
@@ -159,7 +159,7 @@ static struct mm_region early_map[] = {
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+	{ CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
 	  SYS_FSL_OCRAM_SPACE_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 	},
@@ -168,7 +168,7 @@ static struct mm_region early_map[] = {
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
+	{ CFG_SYS_FSL_QSPI_BASE, CFG_SYS_FSL_QSPI_BASE,
 	  CONFIG_SYS_FSL_QSPI_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 	},
@@ -204,7 +204,7 @@ static struct mm_region final_map[] = {
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+	{ CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
 	  SYS_FSL_OCRAM_SPACE_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 	},
@@ -213,12 +213,12 @@ static struct mm_region final_map[] = {
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 	  PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 	},
-	{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+	{ CFG_SYS_FSL_QSPI_BASE1, CFG_SYS_FSL_QSPI_BASE1,
 	  CONFIG_SYS_FSL_QSPI_SIZE1,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
+	{ CFG_SYS_FSL_QSPI_BASE2, CFG_SYS_FSL_QSPI_BASE2,
 	  CONFIG_SYS_FSL_QSPI_SIZE2,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
@@ -333,7 +333,7 @@ static struct mm_region final_map[] = {
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+	{ CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
 	  SYS_FSL_OCRAM_SPACE_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 	},
@@ -342,7 +342,7 @@ static struct mm_region final_map[] = {
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 	},
-	{ CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
+	{ CFG_SYS_FSL_QSPI_BASE, CFG_SYS_FSL_QSPI_BASE,
 	  CONFIG_SYS_FSL_QSPI_SIZE,
 	  PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 	  PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
@@ -401,7 +401,7 @@ struct mm_region *mem_map = early_map;
 
 void cpu_name(char *name)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 	unsigned int i, svr, ver;
 
 	svr = gur_in32(&gur->svr);
@@ -430,7 +430,7 @@ void cpu_name(char *name)
 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 /*
  * To start MMU before DDR is available, we create MMU table in SRAM.
- * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
+ * The base address of SRAM is CFG_SYS_FSL_OCRAM_BASE. We use three
  * levels of translation tables here to cover 40-bit address space.
  * We use 4KB granule size, with 40 bits physical address, T0SZ=24
  * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
@@ -443,7 +443,7 @@ static inline void early_mmu_setup(void)
 
 	/* global data is already setup, no allocation yet */
 	if (el == 3)
-		gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
+		gd->arch.tlb_addr = CFG_SYS_FSL_OCRAM_BASE;
 	else
 		gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
 	gd->arch.tlb_fillptr = gd->arch.tlb_addr;
@@ -466,7 +466,7 @@ static void fix_pcie_mmu_map(void)
 #ifdef CONFIG_ARCH_LS2080A
 	unsigned int i;
 	u32 svr, ver;
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 
 	svr = gur_in32(&gur->svr);
 	ver = SVR_SOC_VER(svr);
@@ -775,7 +775,7 @@ enum boot_src get_boot_src(void)
 #if defined(CONFIG_FSL_LSCH3)
 	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 #elif defined(CONFIG_FSL_LSCH2)
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 #endif
 
 	if (current_el() == 2) {
@@ -863,7 +863,7 @@ enum env_location arch_env_get_location(enum env_operation op, int prio)
 
 u32 initiator_type(u32 cluster, int init_id)
 {
-	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 	u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
 	u32 type = 0;
 
@@ -876,7 +876,7 @@ u32 initiator_type(u32 cluster, int init_id)
 
 u32 cpu_pos_mask(void)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 	int i = 0;
 	u32 cluster, type, mask = 0;
 
@@ -897,7 +897,7 @@ u32 cpu_pos_mask(void)
 
 u32 cpu_mask(void)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 	int i = 0, count = 0;
 	u32 cluster, type, mask = 0;
 
@@ -930,7 +930,7 @@ int cpu_numcores(void)
 int fsl_qoriq_core_to_cluster(unsigned int core)
 {
 	struct ccsr_gur __iomem *gur =
-		(void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
+		(void __iomem *)(CFG_SYS_FSL_GUTS_ADDR);
 	int i = 0, count = 0;
 	u32 cluster;
 
@@ -954,7 +954,7 @@ int fsl_qoriq_core_to_cluster(unsigned int core)
 u32 fsl_qoriq_core_to_type(unsigned int core)
 {
 	struct ccsr_gur __iomem *gur =
-		(void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
+		(void __iomem *)(CFG_SYS_FSL_GUTS_ADDR);
 	int i = 0, count = 0;
 	u32 cluster, type;
 
@@ -979,7 +979,7 @@ u32 fsl_qoriq_core_to_type(unsigned int core)
 #ifndef CONFIG_FSL_LSCH3
 uint get_svr(void)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 
 	return gur_in32(&gur->svr);
 }
@@ -988,7 +988,7 @@ uint get_svr(void)
 #ifdef CONFIG_DISPLAY_CPUINFO
 int print_cpuinfo(void)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 	struct sys_info sysinfo;
 	char buf[32];
 	unsigned int i, core;
@@ -1179,9 +1179,9 @@ int arch_early_init_r(void)
 
 int timer_init(void)
 {
-	u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
+	u32 __iomem *cntcr = (u32 *)CFG_SYS_FSL_TIMER_ADDR;
 #ifdef CONFIG_FSL_LSCH3
-	u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
+	u32 __iomem *cltbenr = (u32 *)CFG_SYS_FSL_PMU_CLTBENR;
 #endif
 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
 	defined(CONFIG_ARCH_LS1028A)
@@ -1230,7 +1230,7 @@ int timer_init(void)
 }
 
 #if !CONFIG_IS_ENABLED(SYSRESET)
-__efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
+__efi_runtime_data u32 __iomem *rstcr = (u32 *)CFG_SYS_FSL_RST_ADDR;
 
 void __efi_runtime reset_cpu(void)
 {
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 427de1cb33..ee734577fc 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -171,9 +171,9 @@ static void fdt_fixup_gic(void *blob)
 {
 	int offset, err;
 	u64 reg[8];
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 	unsigned int val;
-	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+	struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
 	int align_64k = 0;
 
 	val = gur_in32(&gur->svr);
@@ -355,7 +355,7 @@ static int _fdt_fixup_pci_msi(void *blob, const char *name, int rev)
 
 static void fdt_fixup_msi(void *blob)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 	unsigned int rev;
 
 	rev = gur_in32(&gur->svr);
@@ -620,7 +620,7 @@ void fdt_fixup_pfe_firmware(void *blob)
 
 void ft_cpu_setup(void *blob, struct bd_info *bd)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 	unsigned int svr = gur_in32(&gur->svr);
 
 	/* delete crypto node if not on an E-processor */
@@ -635,7 +635,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
 		fdt_fixup_kaslr(blob);
 #endif
 
-		sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+		sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
 		fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
 	}
 #endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
index 60769e139e..1541dfb3ec 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
@@ -40,7 +40,7 @@ int is_serdes_configured(enum srds_prtcl device)
 
 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 	u32 cfg = gur_in32(&gur->rcwsr[4]);
 	int i;
 
@@ -76,7 +76,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 
 int get_serdes_protocol(void)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 	u32 cfg = gur_in32(&gur->rcwsr[4]) &
 			  FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
 	cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
@@ -101,7 +101,7 @@ const char *serdes_clock_to_string(u32 clock)
 void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
 		 u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
 {
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 	u32 cfg;
 	int lane;
 
@@ -142,7 +142,7 @@ __weak int set_serdes_volt(int svdd)
 
 int setup_serdes_volt(u32 svdd)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 	struct ccsr_serdes *serdes1_base;
 #ifdef CONFIG_SYS_FSL_SRDS_2
 	struct ccsr_serdes *serdes2_base;
@@ -168,7 +168,7 @@ int setup_serdes_volt(u32 svdd)
 	if (svdd_cur == svdd_tar)
 		return 0;
 
-	serdes1_base = (void *)CONFIG_SYS_FSL_SERDES_ADDR;
+	serdes1_base = (void *)CFG_SYS_FSL_SERDES_ADDR;
 #ifdef CONFIG_SYS_FSL_SRDS_2
 	serdes2_base = (void *)serdes1_base + 0x10000;
 #endif
@@ -406,14 +406,14 @@ void fsl_serdes_init(void)
 {
 #ifdef CONFIG_SYS_FSL_SRDS_1
 	serdes_init(FSL_SRDS_1,
-		    CONFIG_SYS_FSL_SERDES_ADDR,
+		    CFG_SYS_FSL_SERDES_ADDR,
 		    FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK,
 		    FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT,
 		    serdes1_prtcl_map);
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
 	serdes_init(FSL_SRDS_2,
-		    CONFIG_SYS_FSL_SERDES_ADDR,
+		    CFG_SYS_FSL_SERDES_ADDR,
 		    FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK,
 		    FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT,
 		    serdes2_prtcl_map);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 898ed09b31..6440ce714f 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 void get_sys_info(struct sys_info *sys_info)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 /* rcw_tmp is needed to get FMAN clock, or to get cluster group A
  * mux 2 clock for LS1043A/LS1046A.
  */
@@ -29,7 +29,7 @@ void get_sys_info(struct sys_info *sys_info)
 	    defined(CONFIG_ARCH_LS1043A)
 	u32 rcw_tmp;
 #endif
-	struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
+	struct ccsr_clk *clk = (void *)(CFG_SYS_FSL_CLK_ADDR);
 	unsigned int cpu;
 	const u8 core_cplx_pll[8] = {
 		[0] = 0,	/* CC1 PPL / 1 */
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
index 181bd9c1b4..c0efc341af 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
@@ -86,7 +86,7 @@ int is_serdes_configured(enum srds_prtcl device)
 
 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 	u32 cfg = 0;
 	int i;
 
@@ -134,7 +134,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
 void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
 		 u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
 {
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 	u32 cfg;
 	int lane;
 
@@ -399,18 +399,18 @@ static void do_pll_lock(u32 cfg,
 
 int setup_serdes_volt(u32 svdd)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 	struct ccsr_serdes __iomem *serdes1_base =
-			(void *)CONFIG_SYS_FSL_LSCH3_SERDES_ADDR;
+			(void *)CFG_SYS_FSL_LSCH3_SERDES_ADDR;
 	u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
 #ifdef CONFIG_SYS_FSL_SRDS_2
 	struct ccsr_serdes __iomem *serdes2_base =
-			(void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
+			(void *)(CFG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
 	u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
 #endif
 #ifdef CONFIG_SYS_NXP_SRDS_3
 	struct ccsr_serdes __iomem *serdes3_base =
-			(void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000);
+			(void *)(CFG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000);
 	u32 cfg_rcwsrds3 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
 #endif
 	u32 cfg_tmp;
@@ -585,7 +585,7 @@ void fsl_serdes_init(void)
 
 #ifdef CONFIG_SYS_FSL_SRDS_1
 	serdes_init(FSL_SRDS_1,
-		    CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
+		    CFG_SYS_FSL_LSCH3_SERDES_ADDR,
 		    FSL_CHASSIS3_SRDS1_REGSR,
 		    FSL_CHASSIS3_SRDS1_PRTCL_MASK,
 		    FSL_CHASSIS3_SRDS1_PRTCL_SHIFT,
@@ -593,7 +593,7 @@ void fsl_serdes_init(void)
 #endif
 #ifdef CONFIG_SYS_FSL_SRDS_2
 	serdes_init(FSL_SRDS_2,
-		    CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
+		    CFG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
 		    FSL_CHASSIS3_SRDS2_REGSR,
 		    FSL_CHASSIS3_SRDS2_PRTCL_MASK,
 		    FSL_CHASSIS3_SRDS2_PRTCL_SHIFT,
@@ -601,7 +601,7 @@ void fsl_serdes_init(void)
 #endif
 #ifdef CONFIG_SYS_NXP_SRDS_3
 	serdes_init(NXP_SRDS_3,
-		    CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000,
+		    CFG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000,
 		    FSL_CHASSIS3_SRDS3_REGSR,
 		    FSL_CHASSIS3_SRDS3_PRTCL_MASK,
 		    FSL_CHASSIS3_SRDS3_PRTCL_SHIFT,
@@ -611,7 +611,7 @@ void fsl_serdes_init(void)
 
 int serdes_set_env(int sd, int rcwsr, int sd_prctl_mask, int sd_prctl_shift)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 	char scfg[16], snum[16];
 	int cfgr = 0;
 	u32 cfg;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
index 58080d0047..137778dc13 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -23,13 +23,13 @@ DECLARE_GLOBAL_DATA_PTR;
 
 void get_sys_info(struct sys_info *sys_info)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 	struct ccsr_clk_cluster_group __iomem *clk_grp[2] = {
-		(void *)(CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR),
-		(void *)(CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR)
+		(void *)(CFG_SYS_FSL_CH3_CLK_GRPA_ADDR),
+		(void *)(CFG_SYS_FSL_CH3_CLK_GRPB_ADDR)
 	};
 	struct ccsr_clk_ctrl __iomem *clk_ctrl =
-		(void *)(CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR);
+		(void *)(CFG_SYS_FSL_CH3_CLK_CTRL_ADDR);
 	unsigned int cpu;
 	const u8 core_cplx_pll[16] = {
 		[0] = 0,	/* CC1 PPL / 1 */
@@ -68,7 +68,7 @@ void get_sys_info(struct sys_info *sys_info)
 	uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
 	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
 	unsigned long sysclk = get_board_sys_clk();
-	int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
+	int cc_group[12] = CFG_SYS_FSL_CLUSTER_CLOCKS;
 	u32 c_pll_sel, cplx_pll;
 	void *offset;
 
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
index 2d87281ec2..e972603f24 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
@@ -27,7 +27,7 @@ static void set_icid(struct icid_id_table *tbl, int size)
 void set_fman_icids(struct fman_icid_id_table *tbl, int size)
 {
 	int i;
-	ccsr_fman_t *fm = (void *)CONFIG_SYS_FSL_FM1_ADDR;
+	ccsr_fman_t *fm = (void *)CFG_SYS_FSL_FM1_ADDR;
 
 	for (i = 0; i < size; i++) {
 		out_be32(&fm->fm_bmi_common.fmbm_ppid[tbl[i].port_id - 1],
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 87410c73a9..4358c6ed11 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -325,8 +325,8 @@ ENDPROC(fsl_ocram_init)
 
 ENTRY(fsl_clear_ocram)
 /* Clear OCRAM */
-	ldr	x0, =CONFIG_SYS_FSL_OCRAM_BASE
-	ldr	x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE)
+	ldr	x0, =CFG_SYS_FSL_OCRAM_BASE
+	ldr	x1, =(CFG_SYS_FSL_OCRAM_BASE + CFG_SYS_FSL_OCRAM_SIZE)
 	mov	x2, #0
 clear_loop:
 	str	x2, [x0]
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
index 26f8a49826..fe667f06c3 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
@@ -53,7 +53,7 @@ static struct serdes_config *serdes_cfg_tbl[] = {
 
 bool soc_has_mac1(void)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 	unsigned int svr = gur_in32(&gur->svr);
 	unsigned int version = SVR_SOC_VER(svr);
 
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
index 7222119149..ce0c46ad0d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
@@ -48,8 +48,8 @@ void update_os_arch_secondary_cores(uint8_t os_arch)
 #ifdef CONFIG_FSL_LSCH3
 static void wake_secondary_core_n(int cluster, int core, int cluster_cores)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-	struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_reset __iomem *rst = (void *)(CFG_SYS_FSL_RST_ADDR);
 	u32 mpidr = 0;
 
 	mpidr = ((cluster << 8) | core);
@@ -73,13 +73,13 @@ static void wake_secondary_core_n(int cluster, int core, int cluster_cores)
 
 int fsl_layerscape_wake_seconday_cores(void)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 #ifdef CONFIG_FSL_LSCH3
-	struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
+	struct ccsr_reset __iomem *rst = (void *)(CFG_SYS_FSL_RST_ADDR);
 	u32 svr, ver, cluster, type;
 	int j = 0, cluster_cores = 0;
 #elif defined(CONFIG_FSL_LSCH2)
-	struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
+	struct ccsr_scfg __iomem *scfg = (void *)(CFG_SYS_FSL_SCFG_ADDR);
 #endif
 	u32 cores, cpu_up_mask = 1;
 	int i, timeout = 10;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
index b9894d41bb..117b7a053c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
@@ -253,7 +253,7 @@ int ppa_init(void)
 #endif
 
 #ifdef CONFIG_FSL_LSCH3
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 	boot_loc_ptr_l = &gur->bootlocptrl;
 	boot_loc_ptr_h = &gur->bootlocptrh;
 
@@ -261,7 +261,7 @@ int ppa_init(void)
 	loadable_l = &gur->scratchrw[4];
 	loadable_h = &gur->scratchrw[5];
 #elif defined(CONFIG_FSL_LSCH2)
-	struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
+	struct ccsr_scfg __iomem *scfg = (void *)(CFG_SYS_FSL_SCFG_ADDR);
 	boot_loc_ptr_l = &scfg->scratchrw[1];
 	boot_loc_ptr_h = &scfg->scratchrw[0];
 
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 515dbe02fd..89a6262c12 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -80,7 +80,7 @@ int ls_gic_rd_tables_init(void *blob)
 
 bool soc_has_dp_ddr(void)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 	u32 svr = gur_in32(&gur->svr);
 
 	/* LS2085A, LS2088A, LS2048A has DP_DDR */
@@ -94,7 +94,7 @@ bool soc_has_dp_ddr(void)
 
 bool soc_has_aiop(void)
 {
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 	u32 svr = gur_in32(&gur->svr);
 
 	/* LS2085A has AIOP */
@@ -249,13 +249,13 @@ static void erratum_a008336(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
 	u32 *eddrtqcr1;
 
-#ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
-	eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
+#ifdef CFG_SYS_FSL_DCSR_DDR_ADDR
+	eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
 	if (fsl_ddr_get_version(0) == 0x50200)
 		out_le32(eddrtqcr1, 0x63b30002);
 #endif
-#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
-	eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
+#ifdef CFG_SYS_FSL_DCSR_DDR2_ADDR
+	eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
 	if (fsl_ddr_get_version(0) == 0x50200)
 		out_le32(eddrtqcr1, 0x63b30002);
 #endif
@@ -271,8 +271,8 @@ static void erratum_a008514(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
 	u32 *eddrtqcr1;
 
-#ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
-	eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
+#ifdef CFG_SYS_FSL_DCSR_DDR3_ADDR
+	eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
 	out_le32(eddrtqcr1, 0x63b20002);
 #endif
 #endif
@@ -412,7 +412,7 @@ void fsl_lsch3_early_init_f(void)
 /* Get VDD in the unit mV from voltage ID */
 int get_core_volt_from_fuse(void)
 {
-	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 	int vdd;
 	u32 fusesr;
 	u8 vid;
@@ -462,7 +462,7 @@ int get_core_volt_from_fuse(void)
 static void erratum_a009660(void)
 {
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660
-	u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
+	u32 *eddrtqcr1 = (void *)CFG_SYS_FSL_SCFG_ADDR + 0x20c;
 	out_be32(eddrtqcr1, 0x63b20042);
 #endif
 }
@@ -473,7 +473,7 @@ static void erratum_a008850_early(void)
 	/* part 1 of 2 */
 	struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
 						CONFIG_SYS_CCI400_OFFSET);
-	struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+	struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
 
 	/* Skip if running at lower exception level */
 	if (current_el() < 3)
@@ -493,7 +493,7 @@ void erratum_a008850_post(void)
 	/* part 2 of 2 */
 	struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
 						CONFIG_SYS_CCI400_OFFSET);
-	struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+	struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
 	u32 tmp;
 
 	/* Skip if running at lower exception level */
@@ -526,21 +526,21 @@ void erratum_a010315(void)
 static void erratum_a010539(void)
 {
 #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
-	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 	u32 porsr1;
 
 	porsr1 = in_be32(&gur->porsr1);
 	porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
 	out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
 		 porsr1);
-	out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
+	out_be32((void *)(CFG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
 #endif
 }
 
 /* Get VDD in the unit mV from voltage ID */
 int get_core_volt_from_fuse(void)
 {
-	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
 	int vdd;
 	u32 fusesr;
 	u8 vid;
@@ -588,7 +588,7 @@ static int setup_core_volt(u32 vdd)
 #ifdef CONFIG_SYS_FSL_DDR
 static void ddr_enable_0v9_volt(bool en)
 {
-	struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+	struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
 	u32 tmp;
 
 	tmp = ddr_in32(&ddr->ddr_cdr1);
@@ -629,7 +629,7 @@ int setup_chip_volt(void)
 #ifdef CONFIG_FSL_PFE
 void init_pfe_scfg_dcfg_regs(void)
 {
-	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
 	u32 ecccr2;
 
 	out_be32(&scfg->pfeasbcr,
@@ -653,7 +653,7 @@ void fsl_lsch2_early_init_f(void)
 {
 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
 					CONFIG_SYS_CCI400_OFFSET);
-	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
 #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
 	enum boot_src src;
 #endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 5824778ca2..ff752c21b1 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -24,7 +24,7 @@
 #define SPL_TLB_SETBACK	0x1000000	/* 16MB under effective memory top */
 
 #ifdef CONFIG_ARCH_LS2080A
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1, 4, 4 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1, 4, 4 }
 #define	SRDS_MAX_LANES	8
 #define CONFIG_SYS_PAGE_SIZE		0x10000
 #ifndef L1_CACHE_BYTES
@@ -32,9 +32,9 @@
 #define L1_CACHE_BYTES		BIT(L1_CACHE_SHIFT)
 #endif
 
-#define CONFIG_SYS_FSL_OCRAM_BASE	0x18000000 /* initial RAM */
+#define CFG_SYS_FSL_OCRAM_BASE	0x18000000 /* initial RAM */
 #define SYS_FSL_OCRAM_SPACE_SIZE	0x00200000 /* 2M space */
-#define CONFIG_SYS_FSL_OCRAM_SIZE	0x00020000 /* Real size 128K */
+#define CFG_SYS_FSL_OCRAM_SIZE	0x00020000 /* Real size 128K */
 
 /* DDR */
 #define CONFIG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
@@ -95,7 +95,7 @@
 #define EPU_EPGCR		0x700060000ULL
 
 #elif defined(CONFIG_ARCH_LS1088A)
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1 }
 #define CONFIG_SYS_PAGE_SIZE		0x10000
 
 #define	SRDS_MAX_LANES	4
@@ -126,9 +126,9 @@
 #define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_DDR_BLOCK1_SIZE
 
 /* DCFG - GUR */
-#define CONFIG_SYS_FSL_OCRAM_BASE	0x18000000 /* initial RAM */
+#define CFG_SYS_FSL_OCRAM_BASE	0x18000000 /* initial RAM */
 #define SYS_FSL_OCRAM_SPACE_SIZE	0x00200000 /* 2M space */
-#define CONFIG_SYS_FSL_OCRAM_SIZE	0x00020000 /* Real size 128K */
+#define CFG_SYS_FSL_OCRAM_SIZE	0x00020000 /* Real size 128K */
 
 /* LX2160A/LX2162A Soc Support */
 #elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
@@ -139,13 +139,13 @@
 #define L1_CACHE_SHIFT		6
 #define L1_CACHE_BYTES		BIT(L1_CACHE_SHIFT)
 #endif
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1, 1, 1, 4, 4, 4, 4 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1, 1, 1, 4, 4, 4, 4 }
 
 #define CONFIG_SYS_PAGE_SIZE			0x10000
 
-#define CONFIG_SYS_FSL_OCRAM_BASE		0x18000000 /* initial RAM */
+#define CFG_SYS_FSL_OCRAM_BASE		0x18000000 /* initial RAM */
 #define SYS_FSL_OCRAM_SPACE_SIZE		0x00200000 /* 2M space */
-#define CONFIG_SYS_FSL_OCRAM_SIZE		0x00040000 /* Real size 256K */
+#define CFG_SYS_FSL_OCRAM_SIZE		0x00040000 /* Real size 256K */
 
 /* DDR */
 #define CONFIG_SYS_DDR_BLOCK1_SIZE		((phys_size_t)2 << 30)
@@ -161,7 +161,7 @@
 /* DCFG - GUR */
 
 #elif defined(CONFIG_ARCH_LS1028A)
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1 }
 #define CONFIG_FSL_TZASC_400
 
 /* TZ Protection Controller Definitions */
@@ -180,9 +180,9 @@
 #define	SRDS_MAX_LANES	4
 #define	SRDS_BITS_PER_LANE	4
 
-#define CONFIG_SYS_FSL_OCRAM_BASE		0x18000000 /* initial RAM */
+#define CFG_SYS_FSL_OCRAM_BASE		0x18000000 /* initial RAM */
 #define SYS_FSL_OCRAM_SPACE_SIZE		0x00200000 /* 2M */
-#define CONFIG_SYS_FSL_OCRAM_SIZE		0x00040000 /* Real size 256K */
+#define CFG_SYS_FSL_OCRAM_SIZE		0x00040000 /* Real size 256K */
 
 /* Generic Interrupt Controller Definitions */
 #define GICD_BASE				0x06000000
@@ -200,9 +200,9 @@
 /* DCFG - GUR */
 
 #elif defined(CONFIG_FSL_LSCH2)
-#define CONFIG_SYS_FSL_OCRAM_BASE		0x10000000 /* initial RAM */
+#define CFG_SYS_FSL_OCRAM_BASE		0x10000000 /* initial RAM */
 #define SYS_FSL_OCRAM_SPACE_SIZE		0x00200000 /* 2M space */
-#define CONFIG_SYS_FSL_OCRAM_SIZE		0x00020000 /* Real size 128K */
+#define CFG_SYS_FSL_OCRAM_SIZE		0x00020000 /* Real size 128K */
 
 #define DCSR_DCFG_SBEESR2			0x20140534
 #define DCSR_DCFG_MBEESR2			0x20140544
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index c51b65ea36..4db479140e 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -10,7 +10,7 @@
 #ifdef CONFIG_FSL_LSCH3
 #define CONFIG_SYS_FSL_CCSR_BASE	0x00000000
 #define CONFIG_SYS_FSL_CCSR_SIZE	0x10000000
-#define CONFIG_SYS_FSL_QSPI_BASE1	0x20000000
+#define CFG_SYS_FSL_QSPI_BASE1	0x20000000
 #define CONFIG_SYS_FSL_QSPI_SIZE1	0x10000000
 #ifndef CONFIG_NXP_LSCH3_2
 #define CONFIG_SYS_FSL_IFC_BASE1	0x30000000
@@ -19,7 +19,7 @@
 #endif
 #define CONFIG_SYS_FSL_DRAM_BASE1	0x80000000
 #define CONFIG_SYS_FSL_DRAM_SIZE1	0x80000000
-#define CONFIG_SYS_FSL_QSPI_BASE2	0x400000000
+#define CFG_SYS_FSL_QSPI_BASE2	0x400000000
 #define CONFIG_SYS_FSL_QSPI_SIZE2	0x100000000
 #ifndef CONFIG_NXP_LSCH3_2
 #define CONFIG_SYS_FSL_IFC_BASE2	0x500000000
@@ -73,7 +73,7 @@
 #define CONFIG_SYS_FSL_CCSR_SIZE	0xf000000
 #define CONFIG_SYS_FSL_DCSR_BASE	0x20000000
 #define CONFIG_SYS_FSL_DCSR_SIZE	0x4000000
-#define CONFIG_SYS_FSL_QSPI_BASE	0x40000000
+#define CFG_SYS_FSL_QSPI_BASE	0x40000000
 #define CONFIG_SYS_FSL_QSPI_SIZE	0x20000000
 #define CONFIG_SYS_FSL_IFC_BASE		0x60000000
 #define CONFIG_SYS_FSL_IFC_SIZE		0x20000000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
index 8af0d35d27..9cddb41a89 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
@@ -70,7 +70,7 @@ void fdt_fixup_icid(void *blob);
 
 #define SET_SCFG_ICID(compat, streamid, name, compataddr) \
 	SET_ICID_ENTRY(compat, streamid, (((streamid) << 24) | (1 << 23)), \
-		offsetof(struct ccsr_scfg, name) + CONFIG_SYS_FSL_SCFG_ADDR, \
+		offsetof(struct ccsr_scfg, name) + CFG_SYS_FSL_SCFG_ADDR, \
 		compataddr, SCFG_IS_LE)
 
 #define SET_USB_ICID(usb_num, compat, streamid) \
@@ -83,7 +83,7 @@ void fdt_fixup_icid(void *blob);
 
 #define SET_SDHC_ICID(streamid) \
 	SET_SCFG_ICID("fsl,esdhc", streamid, sdhc_icid,\
-		CONFIG_SYS_FSL_ESDHC_ADDR)
+		CFG_SYS_FSL_ESDHC_ADDR)
 
 #define SET_EDMA_ICID(streamid) \
 	SET_SCFG_ICID("fsl,vf610-edma", streamid, edma_icid,\
@@ -102,14 +102,14 @@ void fdt_fixup_icid(void *blob);
 #define SET_QMAN_ICID(streamid) \
 	SET_ICID_ENTRY("fsl,qman", streamid, streamid, \
 		offsetof(struct ccsr_qman, liodnr) + \
-		CONFIG_SYS_FSL_QMAN_ADDR, \
-		CONFIG_SYS_FSL_QMAN_ADDR, false)
+		CFG_SYS_FSL_QMAN_ADDR, \
+		CFG_SYS_FSL_QMAN_ADDR, false)
 
 #define SET_BMAN_ICID(streamid) \
 	SET_ICID_ENTRY("fsl,bman", streamid, streamid, \
 		offsetof(struct ccsr_bman, liodnr) + \
-		CONFIG_SYS_FSL_BMAN_ADDR, \
-		CONFIG_SYS_FSL_BMAN_ADDR, false)
+		CFG_SYS_FSL_BMAN_ADDR, \
+		CFG_SYS_FSL_BMAN_ADDR, false)
 
 #define SET_FMAN_ICID_ENTRY(_port_id, streamid) \
 	{ .port_id = (_port_id), .icid = (streamid) }
@@ -119,8 +119,8 @@ void fdt_fixup_icid(void *blob);
 #define SET_SEC_QI_ICID(streamid) \
 	SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
 		0, offsetof(ccsr_sec_t, qilcr_ls) + \
-		CONFIG_SYS_FSL_SEC_ADDR, \
-		CONFIG_SYS_FSL_SEC_ADDR, SEC_IS_LE)
+		CFG_SYS_FSL_SEC_ADDR, \
+		CFG_SYS_FSL_SEC_ADDR, SEC_IS_LE)
 
 extern struct fman_icid_id_table fman_icid_tbl[];
 extern int fman_icid_tbl_sz;
@@ -137,7 +137,7 @@ extern int fman_icid_tbl_sz;
 
 #define SET_GUR_ICID(compat, streamid, name, compataddr) \
 	SET_ICID_ENTRY(compat, streamid, streamid, \
-		offsetof(struct ccsr_gur, name) + CONFIG_SYS_FSL_GUTS_ADDR, \
+		offsetof(struct ccsr_gur, name) + CFG_SYS_FSL_GUTS_ADDR, \
 		compataddr, GUR_IS_LE)
 
 #define SET_USB_ICID(usb_num, compat, streamid) \
@@ -180,24 +180,24 @@ extern int fman_icid_tbl_sz;
 	SET_ICID_ENTRY( \
 		(CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) && \
 		(FSL_SEC_JR##jr_num##_OFFSET ==  \
-			SEC_JR3_OFFSET + CONFIG_SYS_FSL_SEC_OFFSET) \
+			SEC_JR3_OFFSET + CFG_SYS_FSL_SEC_OFFSET) \
 			? NULL \
 			: "fsl,sec-v4.0-job-ring"), \
 		streamid, \
 		SEC_ICID_REG_VAL(streamid), \
 		offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \
-		CONFIG_SYS_FSL_SEC_ADDR, \
+		CFG_SYS_FSL_SEC_ADDR, \
 		FSL_SEC_JR##jr_num##_BASE_ADDR, SEC_IS_LE)
 
 #define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \
 	SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
 		offsetof(ccsr_sec_t, decoliodnr[deco_num].ls) + \
-		CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
+		CFG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
 
 #define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \
 	SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
 		offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \
-		CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
+		CFG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
 
 extern struct icid_id_table icid_tbl[];
 extern int icid_tbl_sz;
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 2b73647ab4..e8bd8d2713 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -14,18 +14,18 @@
 #define CONFIG_SYS_DCSRBAR			0x20000000
 #define CONFIG_SYS_DCSR_DCFG_ADDR	(CONFIG_SYS_DCSRBAR + 0x00140000)
 
-#define CONFIG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
+#define CFG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
 #define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x00530000)
 #define SYS_FSL_QSPI_ADDR			(CONFIG_SYS_IMMR + 0x00550000)
-#define CONFIG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x00560000)
-#define CONFIG_SYS_FSL_CSU_ADDR			(CONFIG_SYS_IMMR + 0x00510000)
-#define CONFIG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00ee0000)
-#define CONFIG_SYS_FSL_RST_ADDR			(CONFIG_SYS_IMMR + 0x00ee00b0)
-#define CONFIG_SYS_FSL_SCFG_ADDR		(CONFIG_SYS_IMMR + 0x00570000)
-#define CONFIG_SYS_FSL_BMAN_ADDR		(CONFIG_SYS_IMMR + 0x00890000)
-#define CONFIG_SYS_FSL_QMAN_ADDR		(CONFIG_SYS_IMMR + 0x00880000)
-#define CONFIG_SYS_FSL_SERDES_ADDR		(CONFIG_SYS_IMMR + 0x00ea0000)
-#define CONFIG_SYS_FSL_CLK_ADDR			(CONFIG_SYS_IMMR + 0x00ee1000)
+#define CFG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x00560000)
+#define CFG_SYS_FSL_CSU_ADDR			(CONFIG_SYS_IMMR + 0x00510000)
+#define CFG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00ee0000)
+#define CFG_SYS_FSL_RST_ADDR			(CONFIG_SYS_IMMR + 0x00ee00b0)
+#define CFG_SYS_FSL_SCFG_ADDR		(CONFIG_SYS_IMMR + 0x00570000)
+#define CFG_SYS_FSL_BMAN_ADDR		(CONFIG_SYS_IMMR + 0x00890000)
+#define CFG_SYS_FSL_QMAN_ADDR		(CONFIG_SYS_IMMR + 0x00880000)
+#define CFG_SYS_FSL_SERDES_ADDR		(CONFIG_SYS_IMMR + 0x00ea0000)
+#define CFG_SYS_FSL_CLK_ADDR			(CONFIG_SYS_IMMR + 0x00ee1000)
 #define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011c0500)
 #define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011c0600)
 #define CONFIG_SYS_NS16550_COM3			(CONFIG_SYS_IMMR + 0x011d0500)
@@ -65,7 +65,7 @@
 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 #define CONFIG_SYS_QMAN_SWP_ISDR_REG	0x3680
 
-#define CONFIG_SYS_FSL_TIMER_ADDR		0x02b00000
+#define CFG_SYS_FSL_TIMER_ADDR		0x02b00000
 
 #define I2C1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01180000)
 #define I2C2_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01190000)
@@ -165,24 +165,24 @@ struct sys_info {
 	unsigned long freq_qman;
 };
 
-#define CONFIG_SYS_FSL_FM1_OFFSET		0xa00000
+#define CFG_SYS_FSL_FM1_OFFSET		0xa00000
 
-#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET	0xae0000
-#define CONFIG_SYS_FSL_FM1_ADDR			\
-		(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
-#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR		\
-		(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
+#define CFG_SYS_FSL_FM1_DTSEC1_OFFSET	0xae0000
+#define CFG_SYS_FSL_FM1_ADDR			\
+		(CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_OFFSET)
+#define CFG_SYS_FSL_FM1_DTSEC1_ADDR		\
+		(CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_DTSEC1_OFFSET)
 
-#define CONFIG_SYS_FSL_SEC_OFFSET		0x700000ull
-#define CONFIG_SYS_FSL_JR0_OFFSET		0x710000ull
-#define FSL_SEC_JR0_OFFSET			CONFIG_SYS_FSL_JR0_OFFSET
+#define CFG_SYS_FSL_SEC_OFFSET		0x700000ull
+#define CFG_SYS_FSL_JR0_OFFSET		0x710000ull
+#define FSL_SEC_JR0_OFFSET			CFG_SYS_FSL_JR0_OFFSET
 #define FSL_SEC_JR1_OFFSET			0x720000ull
 #define FSL_SEC_JR2_OFFSET			0x730000ull
 #define FSL_SEC_JR3_OFFSET			0x740000ull
-#define CONFIG_SYS_FSL_SEC_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
+#define CFG_SYS_FSL_SEC_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_FSL_JR0_OFFSET)
 #define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET)
 #define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET)
 #define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 570397b3c0..f1ffb2327d 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -9,19 +9,19 @@
 #ifndef __ARCH_FSL_LSCH3_IMMAP_H_
 #define __ARCH_FSL_LSCH3_IMMAP_H_
 
-#define CONFIG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
-#define CONFIG_SYS_FSL_DDR2_ADDR		(CONFIG_SYS_IMMR + 0x00090000)
-#define CONFIG_SYS_FSL_DDR3_ADDR		0x08210000
-#define CONFIG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00E00000)
-#define CONFIG_SYS_FSL_PMU_ADDR			(CONFIG_SYS_IMMR + 0x00E30000)
+#define CFG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
+#define CFG_SYS_FSL_DDR2_ADDR		(CONFIG_SYS_IMMR + 0x00090000)
+#define CFG_SYS_FSL_DDR3_ADDR		0x08210000
+#define CFG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00E00000)
+#define CFG_SYS_FSL_PMU_ADDR			(CONFIG_SYS_IMMR + 0x00E30000)
 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
-#define CONFIG_SYS_FSL_RST_ADDR			(CONFIG_SYS_IMMR + 0x00e88180)
+#define CFG_SYS_FSL_RST_ADDR			(CONFIG_SYS_IMMR + 0x00e88180)
 #else
-#define CONFIG_SYS_FSL_RST_ADDR			(CONFIG_SYS_IMMR + 0x00E60000)
+#define CFG_SYS_FSL_RST_ADDR			(CONFIG_SYS_IMMR + 0x00E60000)
 #endif
-#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR	(CONFIG_SYS_IMMR + 0x00300000)
-#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR	(CONFIG_SYS_IMMR + 0x00310000)
-#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR	(CONFIG_SYS_IMMR + 0x00370000)
+#define CFG_SYS_FSL_CH3_CLK_GRPA_ADDR	(CONFIG_SYS_IMMR + 0x00300000)
+#define CFG_SYS_FSL_CH3_CLK_GRPB_ADDR	(CONFIG_SYS_IMMR + 0x00310000)
+#define CFG_SYS_FSL_CH3_CLK_CTRL_ADDR	(CONFIG_SYS_IMMR + 0x00370000)
 #ifndef CONFIG_NXP_LSCH3_2
 #define SYS_FSL_QSPI_ADDR			(CONFIG_SYS_IMMR + 0x010c0000)
 #else
@@ -29,8 +29,8 @@
 #define SYS_NXP_FSPI_LUTKEY_BASE_ADDR		0x18
 #define SYS_NXP_FSPI_LUT_BASE_ADDR		0x200
 #endif
-#define CONFIG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x01140000)
-#define FSL_ESDHC1_BASE_ADDR			CONFIG_SYS_FSL_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x01140000)
+#define FSL_ESDHC1_BASE_ADDR			CFG_SYS_FSL_ESDHC_ADDR
 #define FSL_ESDHC2_BASE_ADDR			(CONFIG_SYS_IMMR + 0x01150000)
 #ifndef CONFIG_NXP_LSCH3_2
 #define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x01240000)
@@ -38,20 +38,20 @@
 #define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011C0500)
 #define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011C0600)
 #define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR	0x023d0000
-#define CONFIG_SYS_FSL_TIMER_ADDR		0x023e0000
-#define CONFIG_SYS_FSL_PMU_CLTBENR		(CONFIG_SYS_FSL_PMU_ADDR + \
+#define CFG_SYS_FSL_TIMER_ADDR		0x023e0000
+#define CFG_SYS_FSL_PMU_CLTBENR		(CFG_SYS_FSL_PMU_ADDR + \
 						 0x18A0)
-#define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
-#define FSL_LSCH3_SVR		(CONFIG_SYS_FSL_GUTS_ADDR + 0xA4)
+#define FSL_PMU_PCTBENR_OFFSET (CFG_SYS_FSL_PMU_ADDR + 0x8A0)
+#define FSL_LSCH3_SVR		(CFG_SYS_FSL_GUTS_ADDR + 0xA4)
 
-#define CONFIG_SYS_FSL_WRIOP1_ADDR		(CONFIG_SYS_IMMR + 0x7B80000)
-#define CONFIG_SYS_FSL_WRIOP1_MDIO1	(CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
-#define CONFIG_SYS_FSL_WRIOP1_MDIO2	(CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
-#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR	(CONFIG_SYS_IMMR + 0xEA0000)
+#define CFG_SYS_FSL_WRIOP1_ADDR		(CONFIG_SYS_IMMR + 0x7B80000)
+#define CFG_SYS_FSL_WRIOP1_MDIO1	(CFG_SYS_FSL_WRIOP1_ADDR + 0x16000)
+#define CFG_SYS_FSL_WRIOP1_MDIO2	(CFG_SYS_FSL_WRIOP1_ADDR + 0x17000)
+#define CFG_SYS_FSL_LSCH3_SERDES_ADDR	(CONFIG_SYS_IMMR + 0xEA0000)
 
-#define CONFIG_SYS_FSL_DCSR_DDR_ADDR		0x70012c000ULL
-#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR		0x70012d000ULL
-#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR		0x700132000ULL
+#define CFG_SYS_FSL_DCSR_DDR_ADDR		0x70012c000ULL
+#define CFG_SYS_FSL_DCSR_DDR2_ADDR		0x70012d000ULL
+#define CFG_SYS_FSL_DCSR_DDR3_ADDR		0x700132000ULL
 
 #define I2C1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01000000)
 #define I2C2_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01010000)
@@ -108,16 +108,16 @@
 #define CONFIG_SYS_SFP_ADDR		(CONFIG_SYS_IMMR + 0x00e80200)
 
 /* SEC */
-#define CONFIG_SYS_FSL_SEC_OFFSET		0x07000000ull
-#define CONFIG_SYS_FSL_JR0_OFFSET		0x07010000ull
-#define FSL_SEC_JR0_OFFSET			CONFIG_SYS_FSL_JR0_OFFSET
+#define CFG_SYS_FSL_SEC_OFFSET		0x07000000ull
+#define CFG_SYS_FSL_JR0_OFFSET		0x07010000ull
+#define FSL_SEC_JR0_OFFSET			CFG_SYS_FSL_JR0_OFFSET
 #define FSL_SEC_JR1_OFFSET			0x07020000ull
 #define FSL_SEC_JR2_OFFSET			0x07030000ull
 #define FSL_SEC_JR3_OFFSET			0x07040000ull
-#define CONFIG_SYS_FSL_SEC_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_ADDR \
-	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
+#define CFG_SYS_FSL_SEC_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_ADDR \
+	(CONFIG_SYS_IMMR + CFG_SYS_FSL_JR0_OFFSET)
 #define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET)
 #define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET)
 #define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET)
diff --git a/arch/arm/include/asm/arch-imx8/imx-regs.h b/arch/arm/include/asm/arch-imx8/imx-regs.h
index 3d32b7a02a..f5691620c4 100644
--- a/arch/arm/include/asm/arch-imx8/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8/imx-regs.h
@@ -47,6 +47,6 @@
 #define USB_BASE_ADDR		0x5b0d0000
 #define USB_PHY0_BASE_ADDR	0x5b100000
 
-#define CONFIG_SYS_FSL_SEC_ADDR (0x31400000)
+#define CFG_SYS_FSL_SEC_ADDR (0x31400000)
 
 #endif /* __ASM_ARCH_IMX8_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 29d5baaab8..586847f32e 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -87,12 +87,12 @@
 #define CAAM_ARB_BASE_ADDR              (0x00100000)
 #define CAAM_ARB_END_ADDR               (0x00107FFF)
 #define CAAM_IPS_BASE_ADDR              (0x30900000)
-#define CONFIG_SYS_FSL_SEC_OFFSET       (0)
-#define CONFIG_SYS_FSL_SEC_ADDR         (CAAM_IPS_BASE_ADDR + \
-					 CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_OFFSET       (0x1000)
-#define CONFIG_SYS_FSL_JR0_ADDR         (CONFIG_SYS_FSL_SEC_ADDR + \
-					 CONFIG_SYS_FSL_JR0_OFFSET)
+#define CFG_SYS_FSL_SEC_OFFSET       (0)
+#define CFG_SYS_FSL_SEC_ADDR         (CAAM_IPS_BASE_ADDR + \
+					 CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_OFFSET       (0x1000)
+#define CFG_SYS_FSL_JR0_ADDR         (CFG_SYS_FSL_SEC_ADDR + \
+					 CFG_SYS_FSL_JR0_OFFSET)
 #if !defined(__ASSEMBLY__)
 #include <asm/types.h>
 #include <linux/bitops.h>
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 0e32828b4f..e85918eb7e 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -17,25 +17,25 @@
 #define SYS_FSL_DCSR_RCPM_ADDR	(CONFIG_SYS_DCSRBAR + 0x00222000)
 
 #define SYS_FSL_GIC_ADDR			(CONFIG_SYS_IMMR + 0x00400000)
-#define CONFIG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
-#define CONFIG_SYS_FSL_CSU_ADDR                 (CONFIG_SYS_IMMR + 0x00510000)
+#define CFG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
+#define CFG_SYS_FSL_CSU_ADDR                 (CONFIG_SYS_IMMR + 0x00510000)
 #define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x00530000)
-#define CONFIG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x00560000)
-#define CONFIG_SYS_FSL_SCFG_ADDR		(CONFIG_SYS_IMMR + 0x00570000)
-#define CONFIG_SYS_FSL_SEC_ADDR			(CONFIG_SYS_IMMR + 0x700000)
-#define CONFIG_SYS_FSL_JR0_ADDR			(CONFIG_SYS_IMMR + 0x710000)
+#define CFG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x00560000)
+#define CFG_SYS_FSL_SCFG_ADDR		(CONFIG_SYS_IMMR + 0x00570000)
+#define CFG_SYS_FSL_SEC_ADDR			(CONFIG_SYS_IMMR + 0x700000)
+#define CFG_SYS_FSL_JR0_ADDR			(CONFIG_SYS_IMMR + 0x710000)
 #define CONFIG_SYS_SEC_MON_ADDR			(CONFIG_SYS_IMMR + 0x00e90000)
 #define CONFIG_SYS_SFP_ADDR			(CONFIG_SYS_IMMR + 0x00e80200)
-#define CONFIG_SYS_FSL_SERDES_ADDR		(CONFIG_SYS_IMMR + 0x00ea0000)
-#define CONFIG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00ee0000)
-#define CONFIG_SYS_FSL_LS1_CLK_ADDR		(CONFIG_SYS_IMMR + 0x00ee1000)
-#define CONFIG_SYS_FSL_RCPM_ADDR		(CONFIG_SYS_IMMR + 0x00ee2000)
+#define CFG_SYS_FSL_SERDES_ADDR		(CONFIG_SYS_IMMR + 0x00ea0000)
+#define CFG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00ee0000)
+#define CFG_SYS_FSL_LS1_CLK_ADDR		(CONFIG_SYS_IMMR + 0x00ee1000)
+#define CFG_SYS_FSL_RCPM_ADDR		(CONFIG_SYS_IMMR + 0x00ee2000)
 #define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011c0500)
 #define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011d0500)
 #define CONFIG_SYS_XHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x02100000)
 
-#define CONFIG_SYS_FSL_SEC_OFFSET		0x00700000
-#define CONFIG_SYS_FSL_JR0_OFFSET		0x00710000
+#define CFG_SYS_FSL_SEC_OFFSET		0x00700000
+#define CFG_SYS_FSL_JR0_OFFSET		0x00710000
 #define CONFIG_SYS_TSEC1_OFFSET			0x01d10000
 #define CONFIG_SYS_MDIO1_OFFSET			0x01d24000
 
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
index 93b0a26091..fb5ded8907 100644
--- a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
@@ -29,30 +29,30 @@
 #define SET_SEC_JR_LIODN_ENTRY(jrnum, liodnA, liodnB) \
 	SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB, \
 		offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \
-		CONFIG_SYS_FSL_SEC_OFFSET, \
-		CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum), \
+		CFG_SYS_FSL_SEC_OFFSET, \
+		CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum), \
 	SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\
 		offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \
-		CONFIG_SYS_FSL_SEC_OFFSET, \
-		CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum)
+		CFG_SYS_FSL_SEC_OFFSET, \
+		CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum)
 
 /* This is a bit evil since we treat rtic param as both a string & hex value */
 #define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \
 	SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \
 		liodnA,	\
 		offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
-		CONFIG_SYS_FSL_SEC_OFFSET, \
-		CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
+		CFG_SYS_FSL_SEC_OFFSET, \
+		CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
 	SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \
 		liodnA,	\
 		offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
-		CONFIG_SYS_FSL_SEC_OFFSET, \
-		CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
+		CFG_SYS_FSL_SEC_OFFSET, \
+		CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
 
 #define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \
 	SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \
 		offsetof(ccsr_sec_t, decoliodnr[num].ls) + \
-		CONFIG_SYS_FSL_SEC_OFFSET, 0)
+		CFG_SYS_FSL_SEC_OFFSET, 0)
 
 struct liodn_id_table {
 	const char *compat;
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 56b3a58d47..72944af18a 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -238,12 +238,12 @@
 #endif
 #define ARM_BASE_ADDR		    (ATZ2_BASE_ADDR + 0x40000)
 
-#define CONFIG_SYS_FSL_SEC_OFFSET   0
-#define CONFIG_SYS_FSL_SEC_ADDR     (CAAM_BASE_ADDR + \
-				     CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_OFFSET   0x1000
-#define CONFIG_SYS_FSL_JR0_ADDR     (CAAM_BASE_ADDR + \
-				     CONFIG_SYS_FSL_JR0_OFFSET)
+#define CFG_SYS_FSL_SEC_OFFSET   0
+#define CFG_SYS_FSL_SEC_ADDR     (CAAM_BASE_ADDR + \
+				     CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_OFFSET   0x1000
+#define CFG_SYS_FSL_JR0_ADDR     (CAAM_BASE_ADDR + \
+				     CFG_SYS_FSL_JR0_OFFSET)
 
 #define USB_PL301_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x0000)
 #define USB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x4000)
diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h
index 1e9d11b7a5..c863cd9da3 100644
--- a/arch/arm/include/asm/arch-mx7/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -215,12 +215,12 @@
 
 #define FEC_QUIRK_ENET_MAC
 #define SNVS_LPGPR	0x68
-#define CONFIG_SYS_FSL_SEC_OFFSET       0
-#define CONFIG_SYS_FSL_SEC_ADDR         (CAAM_IPS_BASE_ADDR + \
-					 CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_OFFSET       0x1000
-#define CONFIG_SYS_FSL_JR0_ADDR         (CONFIG_SYS_FSL_SEC_ADDR + \
-					 CONFIG_SYS_FSL_JR0_OFFSET)
+#define CFG_SYS_FSL_SEC_OFFSET       0
+#define CFG_SYS_FSL_SEC_ADDR         (CAAM_IPS_BASE_ADDR + \
+					 CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_OFFSET       0x1000
+#define CFG_SYS_FSL_JR0_ADDR         (CFG_SYS_FSL_SEC_ADDR + \
+					 CFG_SYS_FSL_JR0_OFFSET)
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 #include <asm/mach-imx/regs-lcdif.h>
 #include <asm/types.h>
diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
index ffa170f4d2..33a699ff71 100644
--- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
@@ -228,12 +228,12 @@
 
 #define CAAM_IPS_BASE_ADDR              (AIPS2_BASE + 0x240000) /* 40240000 */
 
-#define CONFIG_SYS_FSL_SEC_OFFSET       0
-#define CONFIG_SYS_FSL_SEC_ADDR         (CAAM_IPS_BASE_ADDR + \
-					 CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_OFFSET       0x1000
-#define CONFIG_SYS_FSL_JR0_ADDR         (CONFIG_SYS_FSL_SEC_ADDR + \
-					 CONFIG_SYS_FSL_JR0_OFFSET)
+#define CFG_SYS_FSL_SEC_OFFSET       0
+#define CFG_SYS_FSL_SEC_ADDR         (CAAM_IPS_BASE_ADDR + \
+					 CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_OFFSET       0x1000
+#define CFG_SYS_FSL_JR0_ADDR         (CFG_SYS_FSL_SEC_ADDR + \
+					 CFG_SYS_FSL_JR0_OFFSET)
 
 #define IOMUXC_DPCR_DDR_DQS0	((IOMUXC_DDR_RBASE + (4 * 32)))
 #define IOMUXC_DPCR_DDR_DQS1	((IOMUXC_DDR_RBASE + (4 * 33)))
diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c
index 04c4b20a84..b65bf874b8 100644
--- a/arch/arm/mach-imx/cmd_dek.c
+++ b/arch/arm/mach-imx/cmd_dek.c
@@ -40,7 +40,7 @@ static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len)
 
 	hab_caam_clock_enable(1);
 
-	u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR +
+	u32 out_jr_size = sec_in32(CFG_SYS_FSL_JR0_ADDR +
 				   FSL_CAAM_ORSR_JRa_OFFSET);
 	if (out_jr_size != FSL_CAAM_MAX_JR_SIZE)
 		sec_init();
diff --git a/arch/arm/mach-imx/cmd_mfgprot.c b/arch/arm/mach-imx/cmd_mfgprot.c
index ec8a8756f7..9576b48dde 100644
--- a/arch/arm/mach-imx/cmd_mfgprot.c
+++ b/arch/arm/mach-imx/cmd_mfgprot.c
@@ -41,7 +41,7 @@ static int do_mfgprot(struct cmd_tbl *cmdtp, int flag, int argc, char *const arg
 	/* Enable HAB clock */
 	hab_caam_clock_enable(1);
 
-	u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR +
+	u32 out_jr_size = sec_in32(CFG_SYS_FSL_JR0_ADDR +
 				   FSL_CAAM_ORSR_JRa_OFFSET);
 
 	if (out_jr_size != FSL_CAAM_MAX_JR_SIZE)
diff --git a/arch/arm/mach-imx/mx7/clock.c b/arch/arm/mach-imx/mx7/clock.c
index 304a030313..88f6fe0274 100644
--- a/arch/arm/mach-imx/mx7/clock.c
+++ b/arch/arm/mach-imx/mx7/clock.c
@@ -30,9 +30,9 @@ DECLARE_GLOBAL_DATA_PTR;
 int get_clocks(void)
 {
 #ifdef CONFIG_FSL_ESDHC_IMX
-#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
+#if CFG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
+#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 #else
 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c
index 6191153917..37d8565c20 100644
--- a/arch/arm/mach-imx/mx7ulp/clock.c
+++ b/arch/arm/mach-imx/mx7ulp/clock.c
@@ -18,9 +18,9 @@ DECLARE_GLOBAL_DATA_PTR;
 int get_clocks(void)
 {
 #ifdef CONFIG_FSL_ESDHC_IMX
-#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC0_RBASE
+#if CFG_SYS_FSL_ESDHC_ADDR == USDHC0_RBASE
 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC1_RBASE
+#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC1_RBASE
 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 #endif
 #endif
diff --git a/arch/arm/mach-imx/speed.c b/arch/arm/mach-imx/speed.c
index b729187ec8..0e81cc880a 100644
--- a/arch/arm/mach-imx/speed.c
+++ b/arch/arm/mach-imx/speed.c
@@ -21,21 +21,21 @@ int get_clocks(void)
 {
 #ifdef CONFIG_FSL_ESDHC_IMX
 #ifdef CONFIG_FSL_USDHC
-#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
+#if CFG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
+#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR
+#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR
 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 #else
 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 #endif
 #else
-#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
+#if CFG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
+#elif CFG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR
+#elif CFG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR
 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 #else
 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);