Merge tag 'xilinx-for-v2023.10-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2023.10-rc1

global:
- Use proper U-Boot project name

Fix sparse warnings in zynqmp-clk, zynqmp handoff, board

cmd:
- Cover incorrect 0 length entries

Versal NET:
- Add bootmode logic
- Support SPP production version
- Add loadpdi command

ZynqMP:
- Clear pmufw node command ID handling
- Change power domain behavior around zynqmp_pmufw_node()
- Fix zynqmp cmd return values and pmufw command
- Fix R5 tcm init and modes

mmc:
- Sync Versal NET emmc DT binding

pcie:
- Add support for ZynqMP PCIe root port

video:
- Add support for ZynqMP DP

tools:
- Fix debug message in relocate-rela

1 files changed, 4 insertions, 4 deletions

diff --git a/arch/arm/mach-versal/mp.c b/arch/arm/mach-versal/mp.c
index 9b0518d6a2..5b850f3f89 100644
--- a/arch/arm/mach-versal/mp.c
+++ b/arch/arm/mach-versal/mp.c
@@ -23,7 +23,7 @@
 #define VERSAL_CRL_RST_CPU_R5_RESET_PGE_MASK	0x10
 #define VERSAL_CRLAPB_CPU_R5_CTRL_CLKACT_MASK	0x1000000
 
-void set_r5_halt_mode(u8 halt, u8 mode)
+static void set_r5_halt_mode(u8 halt, u8 mode)
 {
 	u32 tmp;
 
@@ -44,7 +44,7 @@ void set_r5_halt_mode(u8 halt, u8 mode)
 	}
 }
 
-void set_r5_tcm_mode(u8 mode)
+static void set_r5_tcm_mode(u8 mode)
 {
 	u32 tmp;
 
@@ -62,7 +62,7 @@ void set_r5_tcm_mode(u8 mode)
 	writel(tmp, &rpu_base->rpu_glbl_ctrl);
 }
 
-void release_r5_reset(u8 mode)
+static void release_r5_reset(u8 mode)
 {
 	u32 tmp;
 
@@ -77,7 +77,7 @@ void release_r5_reset(u8 mode)
 	writel(tmp, &crlapb_base->rst_cpu_r5);
 }
 
-void enable_clock_r5(void)
+static void enable_clock_r5(void)
 {
 	u32 tmp;