Merge https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- fix SPL boot issue due to early dbgmcu_init() call
- fix SPL boot issue due to dcache memory region configuration
- add support of CONFIG_ENV_IS_IN_MMC
- add specific SD/eMMC partition for U-Boot enviromnent
- enable env in SPL
- use "env info -q" to remove log during boot
- remove env location override for dh_stm32mp1
- update management of misc_read
- check result of find_mmc_device in stm32prog
- use regulator_set_enable_if_allowed for disabling vdd supply in usbphyc
- enable CMD_ADTIMG flag to handle Android images
- device tree alignment with Linux Kernel v5.8-rc1
- remove hnp-srp-disable for usbotg on dk1
- add reset support to uart nodes on stm32mp15x
- use correct weak function name spl_board_prepare_for_linux
- use cd-gpios for ST and DHSOM boards
- add seeed studio odyssey-stm32mp157c board support
- move ethernet PHY into SoM DT
- add DHSOM based DRC02 board support

1 files changed, 12 insertions, 7 deletions

diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
index 382067190c..b7fcee2b36 100644
--- a/arch/arm/mach-stm32mp/cpu.c
+++ b/arch/arm/mach-stm32mp/cpu.c
@@ -154,15 +154,20 @@ static void security_init(void)
  */
 static void dbgmcu_init(void)
 {
-	setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
-
 	/*
 	 * Freeze IWDG2 if Cortex-A7 is in debug mode
 	 * done in TF-A for TRUSTED boot and
 	 * DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE
 	*/
-	if (!IS_ENABLED(CONFIG_TFABOOT) && bsec_dbgswenable())
+	if (!IS_ENABLED(CONFIG_TFABOOT) && bsec_dbgswenable()) {
+		setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
 		setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
+	}
+}
+
+void spl_board_init(void)
+{
+	dbgmcu_init();
 }
 #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
 
@@ -220,9 +225,10 @@ static void early_enable_caches(void)
 	dcache_enable();
 
 	if (IS_ENABLED(CONFIG_SPL_BUILD))
-		mmu_set_region_dcache_behaviour(STM32_SYSRAM_BASE,
-						STM32_SYSRAM_SIZE,
-						DCACHE_DEFAULT_OPTION);
+		mmu_set_region_dcache_behaviour(
+			ALIGN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE),
+			round_up(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE),
+			DCACHE_DEFAULT_OPTION);
 	else
 		mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE,
 						DCACHE_DEFAULT_OPTION);
@@ -241,7 +247,6 @@ int arch_cpu_init(void)
 	timer_init();
 
 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
-	dbgmcu_init();
 #ifndef CONFIG_TFABOOT
 	security_init();
 	update_bootmode();