diff options
| author | Vikas Manocha <vikas.manocha@st.com> | 2016-02-11 15:47:20 -0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-02-24 18:43:57 -0500 |
| commit | e66c49fa930ed002c507ae0217b4b274c25675fb (patch) | |
| tree | b9da51f6a376e8e3fa2fc556bc6d2b8cc45be29d /arch/arm/mach-stm32/stm32f7/clock.c | |
| parent | 6a12cebd90a752b0214a65b152703ca63a941478 (diff) | |
stm32: add support for stm32f7 & stm32f746 discovery board
This patch adds support for stm32f7 family & stm32f746 board.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Diffstat (limited to 'arch/arm/mach-stm32/stm32f7/clock.c')
| -rw-r--r-- | arch/arm/mach-stm32/stm32f7/clock.c | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/arch/arm/mach-stm32/stm32f7/clock.c b/arch/arm/mach-stm32/stm32f7/clock.c new file mode 100644 index 0000000000..17a715bac9 --- /dev/null +++ b/arch/arm/mach-stm32/stm32f7/clock.c @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2016 + * Vikas Manocha, <vikas.manocha@st.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/rcc.h> +#include <asm/arch/stm32.h> +#include <asm/arch/stm32_periph.h> + +void clock_setup(int peripheral) +{ + switch (peripheral) { + case USART1_CLOCK_CFG: + setbits_le32(RCC_BASE + RCC_APB2ENR, RCC_ENR_USART1EN); + break; + case GPIO_A_CLOCK_CFG: + setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_A_EN); + break; + case GPIO_B_CLOCK_CFG: + setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_B_EN); + break; + case GPIO_C_CLOCK_CFG: + setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_C_EN); + break; + case GPIO_D_CLOCK_CFG: + setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_D_EN); + break; + case GPIO_E_CLOCK_CFG: + setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_E_EN); + break; + case GPIO_F_CLOCK_CFG: + setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_F_EN); + break; + case GPIO_G_CLOCK_CFG: + setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_G_EN); + break; + case GPIO_H_CLOCK_CFG: + setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_H_EN); + break; + case GPIO_I_CLOCK_CFG: + setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_I_EN); + break; + case GPIO_J_CLOCK_CFG: + setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_J_EN); + break; + case GPIO_K_CLOCK_CFG: + setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_K_EN); + break; + default: + break; + } +} |