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authorLey Foon Tan <ley.foon.tan@intel.com>2019-11-08 10:38:20 +0800
committerMarek Vasut <marex@denx.de>2020-01-07 14:38:33 +0100
commitdb5741f7a85ec3ee79b64496172afaa7dc2cb225 (patch)
tree20f749d41ff3c329758f16c1a67f9c5772f35278 /arch/arm/mach-socfpga/scan_manager.c
parentbb25aca1343304e0334e9eebfb9d350eaf276882 (diff)
arm: socfpga: Convert system manager from struct to defines
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get system manager base address from DT node instead of using #define. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Diffstat (limited to 'arch/arm/mach-socfpga/scan_manager.c')
-rw-r--r--arch/arm/mach-socfpga/scan_manager.c6
1 files changed, 2 insertions, 4 deletions
diff --git a/arch/arm/mach-socfpga/scan_manager.c b/arch/arm/mach-socfpga/scan_manager.c
index 52175af48b..f7ee28915e 100644
--- a/arch/arm/mach-socfpga/scan_manager.c
+++ b/arch/arm/mach-socfpga/scan_manager.c
@@ -31,8 +31,6 @@ static const struct socfpga_scan_manager *scan_manager_base =
(void *)(SOCFPGA_SCANMGR_ADDRESS);
static const struct socfpga_freeze_controller *freeze_controller_base =
(void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
-static struct socfpga_system_manager *sys_mgr_base =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
/**
* scan_chain_engine_is_idle() - Check if the JTAG scan chain is idle
@@ -218,7 +216,7 @@ u32 scan_mgr_get_fpga_id(void)
int ret;
/* Enable HPS to talk to JTAG in the FPGA through the System Manager */
- writel(0x1, &sys_mgr_base->scanmgrgrp_ctrl);
+ writel(0x1, socfpga_get_sysmgr_addr() + SYSMGR_GEN5_SCANMGRGRP_CTRL);
/* Enable port 7 */
writel(0x80, &scan_manager_base->en);
@@ -253,7 +251,7 @@ u32 scan_mgr_get_fpga_id(void)
/* Disable all port */
writel(0, &scan_manager_base->en);
- writel(0, &sys_mgr_base->scanmgrgrp_ctrl);
+ writel(0, socfpga_get_sysmgr_addr() + SYSMGR_GEN5_SCANMGRGRP_CTRL);
return id;
}