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authorTom Rini <trini@konsulko.com>2019-04-21 18:59:30 -0400
committerTom Rini <trini@konsulko.com>2019-04-21 18:59:30 -0400
commitb4fde1633e67bb618fd33aad6e6322b7cecf1154 (patch)
treed427acfe3e80e6614a6b9312cb91892dd3dfd8ac /arch/arm/mach-socfpga/include/mach/sdram_s10.h
parent1f4ae66eaab29bfb5d1eb44996f7826c9cd01ed1 (diff)
parente09c1a133155724d3369e150f3ab7b63c875101c (diff)
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
- Various stratix10, gen5 updates
Diffstat (limited to 'arch/arm/mach-socfpga/include/mach/sdram_s10.h')
-rw-r--r--arch/arm/mach-socfpga/include/mach/sdram_s10.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/sdram_s10.h b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
index ca68594445..f39206ca1e 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
@@ -22,6 +22,7 @@ int sdram_calibration_full(void);
#define ECCCTRL1 0x100
#define ECCCTRL2 0x104
#define ERRINTEN 0x110
+#define ERRINTENS 0x114
#define INTMODE 0x11c
#define INTSTAT 0x120
#define AUTOWB_CORRADDR 0x138
@@ -52,6 +53,10 @@ int sdram_calibration_full(void);
#define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3)
#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f
+#define DDR_HMC_ERRINTEN_INTMASK \
+ (DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK | \
+ DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK)
+
/* NOC DDR scheduler */
#define DDR_SCH_ID_COREID 0
#define DDR_SCH_ID_REVID 0x4
@@ -180,4 +185,8 @@ int sdram_calibration_full(void);
#define CALTIMING9_CFG_4_ACT_TO_ACT(x) \
(((x) >> 0) & 0xFF)
+/* Firewall DDR scheduler MPFE */
+#define FW_HMC_ADAPTOR_REG_ADDR 0xf8020004
+#define FW_HMC_ADAPTOR_MPU_MASK BIT(0)
+
#endif /* _SDRAM_S10_H_ */