diff options
| author | Marek Vasut <marex@denx.de> | 2018-04-23 22:49:31 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2018-05-18 10:30:46 +0200 |
| commit | 32f99757f4af48d1e51fdc8817bfed4337dead42 (patch) | |
| tree | af4fe597350d22de14cbf14d550efe1b9a25a70b /arch/arm/mach-socfpga/include/mach/reset_manager.h | |
| parent | 6b49cdd27ed2364543134b12ed6d8351f74b904b (diff) | |
ARM: socfpga: Repair A10 EMAC reset handling
The EMAC reset and PHY mode configuration was never working on the
Arria10 SoC, fix this. This patch pulls out the common code into
misc.c and passes the SoC-specific function call in as a function
pointer.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'arch/arm/mach-socfpga/include/mach/reset_manager.h')
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/reset_manager.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index d3ae80bc27..8ee801c635 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -10,6 +10,8 @@ void reset_cpu(ulong addr); void socfpga_per_reset(u32 reset, int set); void socfpga_per_reset_all(void); +int socfpga_eth_reset_common(void (*resetfn)(const u8 of_reset_id, + const u8 phymode)); #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 |