diff options
| author | Tom Rini <trini@konsulko.com> | 2018-05-20 09:44:05 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-05-20 09:44:05 -0400 |
| commit | 904e546970184d9f5b7e1bde7065b745e67a1bef (patch) | |
| tree | 5873f1c17c89a7db365841e989dc71e22bf09f75 /arch/arm/mach-socfpga/clock_manager.c | |
| parent | 855ff8e6dd58b01930d8b8b726e65310d546a0c9 (diff) | |
| parent | 00f7ae6138ad8b9d859a70d022161297b1bb8049 (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
Diffstat (limited to 'arch/arm/mach-socfpga/clock_manager.c')
| -rw-r--r-- | arch/arm/mach-socfpga/clock_manager.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index bc2c0f8854..59ede59b59 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -20,7 +20,7 @@ void cm_wait_for_lock(u32 mask) do { #if defined(CONFIG_TARGET_SOCFPGA_GEN5) inter_val = readl(&clock_manager_base->inter) & mask; -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#else inter_val = readl(&clock_manager_base->stat) & mask; #endif /* Wait for stable lock */ @@ -51,7 +51,7 @@ int set_cpu_clk_info(void) #if defined(CONFIG_TARGET_SOCFPGA_GEN5) gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000; -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#else gd->bd->bi_ddr_freq = 0; #endif |