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| author | Tom Rini <trini@konsulko.com> | 2021-09-27 09:45:36 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-09-27 09:45:36 -0400 |
| commit | e908d20fcbd847e17345591fc171b59d9a156516 (patch) | |
| tree | def104237fd9b8888a37a5c3378b4ef7e26b6d43 /arch/arm/mach-k3/am6_init.c | |
| parent | bb38d77ca779cc8bdad3d4ceb6cecc687f4987c2 (diff) | |
| parent | 0b9bcf665cd98fe9db0956c894006b250a7d465f (diff) | |
Merge tag 'v2021.10-rc5' into next
Prepare v2021.10-rc5
Diffstat (limited to 'arch/arm/mach-k3/am6_init.c')
| -rw-r--r-- | arch/arm/mach-k3/am6_init.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c index 425b3f93c8..ffb7aaded2 100644 --- a/arch/arm/mach-k3/am6_init.c +++ b/arch/arm/mach-k3/am6_init.c @@ -151,6 +151,19 @@ int fdtdec_board_setup(const void *fdt_blob) return fixup_usb_boot(); } #endif + +static void setup_am654_navss_northbridge(void) +{ + /* + * NB0 is bridge to SRAM and NB1 is bridge to DDR. + * To ensure that SRAM transfers are not stalled due to + * delays during DDR refreshes, SRAM traffic should be higher + * priority (threadmap=2) than DDR traffic (threadmap=0). + */ + writel(0x2, NAVSS0_NBSS_NB0_CFG_BASE + NAVSS_NBSS_THREADMAP); + writel(0x0, NAVSS0_NBSS_NB1_CFG_BASE + NAVSS_NBSS_THREADMAP); +} + void board_init_f(ulong dummy) { #if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS) @@ -168,6 +181,8 @@ void board_init_f(ulong dummy) /* Make all control module registers accessible */ ctrl_mmr_unlock(); + setup_am654_navss_northbridge(); + #ifdef CONFIG_CPU_V7R disable_linefill_optimization(); setup_k3_mpu_regions(); |