diff options
| author | Alice Guo <alice.guo@nxp.com> | 2021-10-29 09:46:29 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2022-02-05 13:38:39 +0100 |
| commit | 0f9b10aaba20696886477f29813d85f39ed32f3e (patch) | |
| tree | 0221c617ff1e47dafc71d7c640fa083811604c83 /arch/arm/mach-imx | |
| parent | 484b306b9e53d39c87b54376fc4468ff5aa34297 (diff) | |
imx8ulp: clock: Support to enable/disable the ADC1 clock
This patch implements enable_adc1_clk() to enable or disable the ADC1
clock on i.MX8ULP.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch/arm/mach-imx')
| -rw-r--r-- | arch/arm/mach-imx/imx8ulp/clock.c | 12 | ||||
| -rw-r--r-- | arch/arm/mach-imx/imx8ulp/pcc.c | 28 |
2 files changed, 39 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c index d03269ac04..961702310c 100644 --- a/arch/arm/mach-imx/imx8ulp/clock.c +++ b/arch/arm/mach-imx/imx8ulp/clock.c @@ -341,6 +341,18 @@ void enable_mipi_dsi_clk(unsigned char enable) } } +void enable_adc1_clk(bool enable) +{ + if (enable) { + pcc_clock_enable(1, ADC1_PCC1_SLOT, false); + pcc_clock_sel(1, ADC1_PCC1_SLOT, CM33_BUSCLK); + pcc_clock_enable(1, ADC1_PCC1_SLOT, true); + pcc_reset_peripheral(1, ADC1_PCC1_SLOT, false); + } else { + pcc_clock_enable(1, ADC1_PCC1_SLOT, false); + } +} + void reset_lcdclk(void) { /* Disable clock and reset dcnano*/ diff --git a/arch/arm/mach-imx/imx8ulp/pcc.c b/arch/arm/mach-imx/imx8ulp/pcc.c index 6145b3ea6a..7909d770af 100644 --- a/arch/arm/mach-imx/imx8ulp/pcc.c +++ b/arch/arm/mach-imx/imx8ulp/pcc.c @@ -15,6 +15,21 @@ #define cgc_clk_TYPES 2 #define cgc_clk_NUM 8 +static enum cgc_clk pcc1_clksrc[][8] = { + { + }, + { + DUMMY0_CLK, + LPOSC, + SOSC_DIV2, + FRO_DIV2, + CM33_BUSCLK, + PLL1_VCO_DIV, + PLL0_PFD2_DIV, + PLL0_PFD1_DIV, + } +}; + static enum cgc_clk pcc3_clksrc[][8] = { { }, @@ -75,6 +90,11 @@ static enum cgc_clk pcc5_clksrc[][8] = { } }; +static struct pcc_entry pcc1_arrays[] = { + {PCC1_RBASE, ADC1_PCC1_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV, PCC_HAS_RST_B}, + {} +}; + static struct pcc_entry pcc3_arrays[] = { {PCC3_RBASE, DMA1_MP_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, {PCC3_RBASE, DMA1_CH0_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B}, @@ -228,6 +248,10 @@ static int find_pcc_entry(int pcc_controller, int pcc_clk_slot, struct pcc_entry int index = 0; switch (pcc_controller) { + case 1: + pcc_array = pcc1_arrays; + *out = &pcc1_arrays[0]; + break; case 3: pcc_array = pcc3_arrays; *out = &pcc3_arrays[0]; @@ -310,7 +334,9 @@ int pcc_clock_sel(int pcc_controller, int pcc_clk_slot, enum cgc_clk src) return -EPERM; } - if (pcc_controller == 3) + if (pcc_controller == 1) + cgc_clk_array = pcc1_clksrc[clksrc_type]; + else if (pcc_controller == 3) cgc_clk_array = pcc3_clksrc[clksrc_type]; else if (pcc_controller == 4) cgc_clk_array = pcc4_clksrc[clksrc_type]; |