diff options
| author | Marek Vasut <marex@denx.de> | 2020-08-05 15:30:43 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2020-08-17 17:55:49 +0200 |
| commit | af50d92ae75cae41dfc330daaad0f8f35a051c78 (patch) | |
| tree | 5756b5e8c2f1b0760a9b6e8c15f3a3997b84bf1f /arch/arm/mach-imx/mx7/ddr.c | |
| parent | 4b44bea701a67e3b83cb82f44fa40485b111d394 (diff) | |
ARM: imx: ddr: Add deskew register programming
Fill is code for programming the DDR_PHY_CMD_DESKEW_CONx registers,
which are optional, but can be used to fill in the byte lane delays.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch/arm/mach-imx/mx7/ddr.c')
| -rw-r--r-- | arch/arm/mach-imx/mx7/ddr.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/mx7/ddr.c b/arch/arm/mach-imx/mx7/ddr.c index 45954ed1ed..cf25569765 100644 --- a/arch/arm/mach-imx/mx7/ddr.c +++ b/arch/arm/mach-imx/mx7/ddr.c @@ -106,6 +106,15 @@ void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val, ~DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK, &ddr_phy_regs->cmd_sdll_con0); writel(ddr_phy_regs_val->offset_lp_con0, &ddr_phy_regs->offset_lp_con0); + writel(ddr_phy_regs_val->cmd_deskew_con0, + &ddr_phy_regs->cmd_deskew_con0); + writel(ddr_phy_regs_val->cmd_deskew_con1, + &ddr_phy_regs->cmd_deskew_con1); + writel(ddr_phy_regs_val->cmd_deskew_con2, + &ddr_phy_regs->cmd_deskew_con2); + writel(ddr_phy_regs_val->cmd_deskew_con3, + &ddr_phy_regs->cmd_deskew_con3); + writel(ddr_phy_regs_val->cmd_lvl_con0, &ddr_phy_regs->cmd_lvl_con0); /* calibration */ for (i = 0; i < calib_param->num_val; i++) |