imx: imx8ulp: Configure XRDC PDAC and MSC for DBD owner=S400 only

This patch is used to support DBD owner fuse changed to S400 only.
The XRDC PDAC2 for LPAV pbridge5 and MSC1/2/3 for GPIO and LPAV are not
configured by S400 default setting.  So these PDAC and MSC are invalid,
only DBD owner can access the corresponding resources.

We have to configure necessary PDAC and MSC for SPL before DDR
initialization.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

1 files changed, 41 insertions, 0 deletions

diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c
index 8db96c1886..56df111bc3 100644
--- a/arch/arm/mach-imx/imx8ulp/rdc.c
+++ b/arch/arm/mach-imx/imx8ulp/rdc.c
@@ -181,6 +181,25 @@ int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm)
 	return 0;
 }
 
+int xrdc_config_msc(u32 msc, u32 index, u32 dom, u32 perm)
+{
+	ulong w0_addr;
+	u32 val;
+
+	if (msc > 2)
+		return -EINVAL;
+
+	w0_addr = XRDC_ADDR + 0x4000 + 0x400 * msc + 0x8 * index;
+
+	val = readl(w0_addr);
+	writel((val & ~(0x7 << (dom * 3))) | (perm << (dom * 3)), w0_addr);
+
+	val = readl(w0_addr + 4);
+	writel(val | BIT(31), w0_addr + 4);
+
+	return 0;
+}
+
 int release_rdc(enum rdc_type type)
 {
 	ulong s_mu_base = 0x27020000UL;
@@ -325,6 +344,28 @@ void xrdc_init_mrc(void)
 	xrdc_config_mrc_w3_w4(6, 0, 0x0, 0x80000FFF);
 }
 
+void xrdc_init_pdac_msc(void)
+{
+	/* Init LPAV PDAC and MSC for DDR init */
+	xrdc_config_pdac(5, 36, 6, 0x7); /* CMC2*/
+	xrdc_config_pdac(5, 36, 7, 0x7);
+	xrdc_config_pdac(5, 37, 6, 0x7); /* SIM2 */
+	xrdc_config_pdac(5, 37, 7, 0x7);
+	xrdc_config_pdac(5, 38, 6, 0x7); /* CGC2 */
+	xrdc_config_pdac(5, 38, 7, 0x7);
+	xrdc_config_pdac(5, 39, 6, 0x7); /* PCC5 */
+	xrdc_config_pdac(5, 39, 7, 0x7);
+
+	xrdc_config_msc(0, 0, 6, 0x7); /* GPIOE */
+	xrdc_config_msc(0, 0, 7, 0x7);
+	xrdc_config_msc(0, 1, 6, 0x7); /* GPIOF */
+	xrdc_config_msc(0, 1, 7, 0x7);
+	xrdc_config_msc(1, 0, 6, 0x7); /* GPIOD */
+	xrdc_config_msc(1, 0, 7, 0x7);
+	xrdc_config_msc(2, 6, 6, 0x7); /* DDR controller */
+	xrdc_config_msc(2, 6, 7, 0x7);
+}
+
 int trdc_mbc_set_access(u32 mbc_x, u32 dom_x, u32 mem_x, u32 blk_x, bool sec_access)
 {
 	struct trdc *trdc_base = (struct trdc *)0x28031000U;