diff options
| author | Ye Li <ye.li@nxp.com> | 2022-04-06 14:30:13 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2022-04-12 17:33:56 +0200 |
| commit | 4ab38f6822d9564da7b85649e6bc7d5c9d603350 (patch) | |
| tree | b6d2bf9c03d739267d2b2243a89ce68e0ac7f38c /arch/arm/mach-imx/imx8ulp/clock.c | |
| parent | a092f33305d8f64c30794305746a1807c55f2063 (diff) | |
imx: imx8ulp_evk: Skip init DDR for reboot in dual boot mode
When M33 is LPAV owner in dual boot, DDR, PCC5, CGC2 won't be reset
during APD reset. So no need to init DDR again after reboot, but need to
reconfigure the PLL4 PFD/PFDDIV/LPAV NIC etc, because kernel may
change or disable some of them.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch/arm/mach-imx/imx8ulp/clock.c')
| -rw-r--r-- | arch/arm/mach-imx/imx8ulp/clock.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c index 46971578a9..69cccafbce 100644 --- a/arch/arm/mach-imx/imx8ulp/clock.c +++ b/arch/arm/mach-imx/imx8ulp/clock.c @@ -101,7 +101,7 @@ void init_clk_ddr(void) writel(0xc0000000, PCC5_LPDDR4_ADDR); /* enable pll4 and ddrclk*/ - cgc2_pll4_init(); + cgc2_pll4_init(true); cgc2_ddrclk_config(4, 1); /* enable ddr pcc */ |