diff options
| author | Ye Li <ye.li@nxp.com> | 2022-04-06 14:30:13 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2022-04-12 17:33:56 +0200 |
| commit | 4ab38f6822d9564da7b85649e6bc7d5c9d603350 (patch) | |
| tree | b6d2bf9c03d739267d2b2243a89ce68e0ac7f38c /arch/arm/mach-imx/imx8ulp/cgc.c | |
| parent | a092f33305d8f64c30794305746a1807c55f2063 (diff) | |
imx: imx8ulp_evk: Skip init DDR for reboot in dual boot mode
When M33 is LPAV owner in dual boot, DDR, PCC5, CGC2 won't be reset
during APD reset. So no need to init DDR again after reboot, but need to
reconfigure the PLL4 PFD/PFDDIV/LPAV NIC etc, because kernel may
change or disable some of them.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch/arm/mach-imx/imx8ulp/cgc.c')
| -rw-r--r-- | arch/arm/mach-imx/imx8ulp/cgc.c | 20 |
1 files changed, 11 insertions, 9 deletions
diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c index 494ddb0f32..ccd977f1a5 100644 --- a/arch/arm/mach-imx/imx8ulp/cgc.c +++ b/arch/arm/mach-imx/imx8ulp/cgc.c @@ -187,7 +187,7 @@ void cgc1_pll3_init(ulong freq) } } -void cgc2_pll4_init(void) +void cgc2_pll4_init(bool pll4_reset) { /* Disable PFD DIV and clear DIV */ writel(0x80808080, &cgc2_regs->pll4div_pfd0); @@ -196,16 +196,18 @@ void cgc2_pll4_init(void) /* Gate off and clear PFD */ writel(0x80808080, &cgc2_regs->pll4pfdcfg); - /* Disable PLL4 */ - writel(0x0, &cgc2_regs->pll4csr); + if (pll4_reset) { + /* Disable PLL4 */ + writel(0x0, &cgc2_regs->pll4csr); - /* Configure PLL4 to 528Mhz and clock source from SOSC */ - writel(22 << 16, &cgc2_regs->pll4cfg); - writel(0x1, &cgc2_regs->pll4csr); + /* Configure PLL4 to 528Mhz and clock source from SOSC */ + writel(22 << 16, &cgc2_regs->pll4cfg); + writel(0x1, &cgc2_regs->pll4csr); - /* wait for PLL4 output valid */ - while (!(readl(&cgc2_regs->pll4csr) & BIT(24))) - ; + /* wait for PLL4 output valid */ + while (!(readl(&cgc2_regs->pll4csr) & BIT(24))) + ; + } /* Enable all 4 PFDs */ setbits_le32(&cgc2_regs->pll4pfdcfg, 18 << 0); /* 528 */ |