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authorMarek Szyprowski <m.szyprowski@samsung.com>2020-06-03 14:43:44 +0200
committerTom Rini <trini@konsulko.com>2020-07-10 14:10:43 -0400
commit814e1a4b8cfd1e78bc7c1d22efa45bcd6a80430e (patch)
treefc4a0ef49bb2f91332964934c8d7c55e10624d17 /arch/arm/mach-bcm283x/include/mach/base.h
parent221c5e42a68e44916af5bacb8a8008ec7ef455d5 (diff)
rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit)
Create a non-cacheable mapping for the 0x600000000 physical memory region, where MMIO registers for the PCIe XHCI controller are instantiated by the PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM 32bit mode, this region is mapped at 0xff800000 CPU virtual address. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Diffstat (limited to 'arch/arm/mach-bcm283x/include/mach/base.h')
-rw-r--r--arch/arm/mach-bcm283x/include/mach/base.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mach-bcm283x/include/mach/base.h b/arch/arm/mach-bcm283x/include/mach/base.h
index c4ae39852f..4ccaf69693 100644
--- a/arch/arm/mach-bcm283x/include/mach/base.h
+++ b/arch/arm/mach-bcm283x/include/mach/base.h
@@ -8,4 +8,12 @@
extern unsigned long rpi_bcm283x_base;
+#ifdef CONFIG_ARMV7_LPAE
+#ifdef CONFIG_TARGET_RPI_4_32B
+#include <addr_map.h>
+#define phys_to_virt addrmap_phys_to_virt
+#define virt_to_phys addrmap_virt_to_phys
+#endif
+#endif
+
#endif