diff options
| author | Tom Rini <trini@konsulko.com> | 2020-05-01 16:43:15 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-05-01 16:43:15 -0400 |
| commit | c693f212c5b0433b3a49a89d87cbff28bf78eb87 (patch) | |
| tree | fba202b549b53e536feb5d7b60e6313074d93a55 /arch/arm/lib/cache-cp15.c | |
| parent | b641dd3ec8dc3f6b18d2fa945ac3ab597063d191 (diff) | |
| parent | 14b7004532a41cbb2dc82cc1a5687e8e88e1ba0d (diff) | |
Merge branch '2020-05-01-master-imports'
- Assorted bug fixes
- Framework for enabling D-CACHE in SPL on ARM
Diffstat (limited to 'arch/arm/lib/cache-cp15.c')
| -rw-r--r-- | arch/arm/lib/cache-cp15.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index f8d20960da..f803d6fb8c 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -61,8 +61,11 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, unsigned long startpt, stoppt; unsigned long upto, end; - end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT; + /* div by 2 before start + size to avoid phys_addr_t overflow */ + end = ALIGN((start / 2) + (size / 2), MMU_SECTION_SIZE / 2) + >> (MMU_SECTION_SHIFT - 1); start = start >> MMU_SECTION_SHIFT; + #ifdef CONFIG_ARMV7_LPAE debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size, option); @@ -91,19 +94,16 @@ __weak void dram_bank_mmu_setup(int bank) bd_t *bd = gd->bd; int i; + /* bd->bi_dram is available only after relocation */ + if ((gd->flags & GD_FLG_RELOC) == 0) + return; + debug("%s: bank: %d\n", __func__, bank); for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) + (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT); - i++) { -#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) - set_section_dcache(i, DCACHE_WRITETHROUGH); -#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) - set_section_dcache(i, DCACHE_WRITEALLOC); -#else - set_section_dcache(i, DCACHE_WRITEBACK); -#endif - } + i++) + set_section_dcache(i, DCACHE_DEFAULT_OPTION); } /* to activate the MMU we need to set up virtual memory: use 1M areas */ |