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| author | Tom Rini <trini@konsulko.com> | 2017-10-01 13:05:53 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-10-01 13:05:53 -0400 |
| commit | 16d4ff76c524fa8b0adb5328a9977b6939cd5416 (patch) | |
| tree | 8b07bc434bb14904afce38003fe7e29ca278c95d /arch/arm/include/asm/arch-rockchip/sys_proto.h | |
| parent | 958046fc78f95a3d28b06980a7eb3ed80123c533 (diff) | |
| parent | e19fa89c9d344201da25a7b67fdd9d6896af6847 (diff) | |
Merge git://git.denx.de/u-boot-rockchip
Diffstat (limited to 'arch/arm/include/asm/arch-rockchip/sys_proto.h')
| -rw-r--r-- | arch/arm/include/asm/arch-rockchip/sys_proto.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-rockchip/sys_proto.h b/arch/arm/include/asm/arch-rockchip/sys_proto.h index 35423e1ba0..e428d59336 100644 --- a/arch/arm/include/asm/arch-rockchip/sys_proto.h +++ b/arch/arm/include/asm/arch-rockchip/sys_proto.h @@ -7,4 +7,27 @@ #ifndef _ASM_ARCH_SYS_PROTO_H #define _ASM_ARCH_SYS_PROTO_H +#ifdef CONFIG_ROCKCHIP_RK3288 +#include <asm/armv7.h> + +static void configure_l2ctlr(void) +{ + uint32_t l2ctlr; + + l2ctlr = read_l2ctlr(); + l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */ + + /* + * Data RAM write latency: 2 cycles + * Data RAM read latency: 2 cycles + * Data RAM setup latency: 1 cycle + * Tag RAM write latency: 1 cycle + * Tag RAM read latency: 1 cycle + * Tag RAM setup latency: 1 cycle + */ + l2ctlr |= (1 << 3 | 1 << 0); + write_l2ctlr(l2ctlr); +} +#endif /* CONFIG_ROCKCHIP_RK3288 */ + #endif /* _ASM_ARCH_SYS_PROTO_H */ |