Merge branch 'master' of git://git.denx.de/u-boot-arm

* 'master' of git://git.denx.de/u-boot-arm: (167 commits)
  OMAP4/5: Change omap4_sdp, omap4_panda, omap5_evm maintainer
  ARM: omap3: Add CONFIG_SPL_BOARD_INIT for CONFIG_SPL_MMC_SUPPORT
  ARM: omap3: Set SPL stack size to 8KB, image to 54KB.
  arm, omap3: fix warm reset serial output on OMAP36xx/AM/DM37xx
  OMAP4: Set fdt_high for OMAP4 devices to enable booting with Device Tree
  omap4: do not enable auxiliary cores
  omap4: do not enable fs-usb module
  omap4: panda: disable uart2 pads during boot
  igep00x0: change mpurate from 500 to auto
  igep00x0: enable the use of a plain text file
  tegra2: trivially enable 13 mhz crystal frequency
  tegra: Enable keyboard for Seaboard
  tegra: Switch on console mux and use environment for console
  tegra: Add tegra keyboard driver
  tegra: fdt: Add keyboard definitions for Seaboard
  tegra: fdt: Add keyboard controller definition
  tegra: Add keyboard support to funcmux
  input: Add support for keyboard matrix decoding from an fdt
  input: Add generic keyboard input handler
  input: Add linux/input.h for key code support
  fdt: Add fdtdec functions to read byte array
  tegra: Enable LP0 on Seaboard
  tegra: fdt: Add EMC data for Tegra2 Seaboard
  tegra: i2c: Add function to find DVC bus
  fdt: tegra: Add EMC node to device tree
  tegra: Add EMC settings for Seaboard
  tegra: Turn off power detect in board init
  tegra: Set up warmboot code on Nvidia boards
  tegra: Setup PMC scratch info from ap20 setup
  tegra: Add warmboot implementation
  tegra: Set up PMU for Nvidia boards
  tegra: Add PMU to manage power supplies
  tegra: Add EMC support for optimal memory timings
  tegra: Add header file for APB_MISC register
  tegra: Add tegra_get_chip_type() to detect SKU
  tegra: Add flow, gp_padctl, fuse, sdram headers
  tegra: Add crypto library for warmboot code
  tegra: Add functions to access low-level Osc/PLL details
  tegra: Move ap20.h header into arch location
  Add AES crypto library
  i2c: Add TPS6586X driver
  Add abs() macro to return absolute value
  fdt: Add function to return next compatible subnode
  fdt: Add function to locate an array in the device tree
  i.MX28: Avoid redefining serial_put[cs]()
  i.MX28: Check if WP detection is implemented at all
  i.MX28: Add battery boot components to SPL
  i.MX28: Reorder battery status functions in SPL
  i.MX28: Add LRADC init to i.MX28 SPL
  i.MX28: Add LRADC register definitions
  i.MX28: Shut down the LCD controller before reset
  i.MX28: Add LCDIF register definitions
  i.MX28: Implement boot pads sampling and reporting
  i.MX28: Improve passing of data from SPL to U-Boot
  M28EVK: Add SD update command
  M28EVK: Implement support for new board V2.0
  FEC: Abstract out register setup
  MX5: PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH exchanged
  i.MX28: Add delay after CPU bypass is cleared
  spi: mxs: Allow other chip selects to work
  spi: mxs: Introduce spi_cs_is_valid()
  mx53loco: Remove unneeded gpio_set_value()
  mx53loco: Add CONFIG_REVISION_TAG
  mx53loco: Turn on VUSB regulator
  mx53loco: Add mc34708 support and set mx53 frequency at 1GHz
  pmic: dialog: Avoid name conflicts
  imx: Add u-boot.imx as target for ARM9 i.MX SOCs
  i.MX2: Include asm/types.h in arch-mx25/imx-regs.h
  imx: usb: There is no such register
  i.MX25: usb: Set PORTSCx register
  imx: nand: Support flash based BBT
  i.MX25: This architecture has a GPIO4 too
  i.MX25: esdhc: Add mxc_get_clock infrastructure
  i.MX6: mx6q_sabrelite: add SATA bindings
  i.MX6: add enable_sata_clock()
  i.MX6: Add ANATOP regulator init
  mx28evk: add NAND support
  USB: ehci-mx6: Fix broken IO access
  M28: Scan only first 512 MB of DRAM to avoid memory wraparound
  Revert "i.MX28: Enable additional DRAM address bits"
  M28: Enable FDT support
  mx53loco: Add support for 1GHz operation for DA9053-based boards
  mx53loco: Allow to print CPU information at a later stage
  mx5: Add clock config interface
  imx-common: Factor out get_ahb_clk()
  i.MX6Q: mx6qsabrelite: Add keypress support to alter boot flow
  mx31pdk: Allow booting a zImage kernel
  mx6qarm2: Allow booting a zImage kernel
  mx6qsabrelite: Allow booting a zImage kernel
  mx28evk: Allow booting a zImage kernel
  m28evk: Allow to booting a dt kernel
  mx28evk: Allow to booting a dt kernel
  mx6qsabrelite: No need to set the direction for GPIO3_23 again
  pmic: Add support for the Dialog DA9053 PMIC
  MX53: mx53loco: Add SATA support
  MX53: Add support to ESG ima3 board
  SATA: add driver for MX5 / MX6 SOCs
  MX53: add function to set SATA clock to internal
  SATA: check for return value from sata functions
  MX5: Add definitions for SATA controller
  NET: fec_mxc.c: Add a way to disable auto negotiation
  Define UART4 and UART5 base addresses
  EXYNOS: Change bits per pixel value proper for u-boot.
  EXYNOS: support TRATS board display function
  LCD: support S6E8AX0 amoled driver based on EXYNOS MIPI DSI
  EXYNOS: support EXYNOS MIPI DSI interface driver.
  EXYNOS: support EXYNOS framebuffer and FIMD display drivers.
  LCD: add data structure for EXYNOS display driver
  EXYNOS: add LCD and MIPI DSI clock interface.
  EXYNOS: definitions of system resgister and power management registers.
  SMDK5250: fix compiler warning
  misc:pmic:samsung Convert TRATS target to use MAX8997 instead of MAX8998
  misc:pmic:max8997 MAX8997 support for PMIC driver
  TRATS: modify the trats's configuration
  ARM: Exynos4: ADC: Universal_C210: Enable LDO4 power line for ADC measurement
  EXYNOS: Rename exynos5_tzpc structure to exynos_tzpc
  arm: ea20: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT
  arm: cam_enc_4xx: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT
  cm-t35: add I2C multi-bus support
  include/configs: Remove CONFIG_SYS_64BIT_STRTOUL
  include/configs: Remove CONFIG_SYS_64BIT_VSPRINTF
  omap3: Introduce weak misc_init_r
  omap730p2: Remove empty misc_init_r
  omap5912osk: Remove empty misc_init_r
  omap4+: Remove CONFIG_ARCH_CPU_INIT
  omap4: Remove CONFIG_SYS_MMC_SET_DEV
  OMAP3: pandora: drop console kernel argument
  OMAP3: pandora: revise GPIO configuration
  ...

1 files changed, 114 insertions, 39 deletions

diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index d811d6ec23..e3f55d2020 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -98,17 +98,6 @@
 #define TCLR_AR			(0x1 << 1)
 #define TCLR_PRE		(0x1 << 5)
 
-/*
- * PRCM
- */
-
-/* PRM */
-#define PRM_BASE		0x4AE06000
-#define PRM_DEVICE_BASE		(PRM_BASE + 0x1B00)
-
-#define PRM_RSTCTRL		PRM_DEVICE_BASE
-#define PRM_RSTCTRL_RESET	0x01
-
 /* Control Module */
 #define LDOSRAM_ACTMODE_VSET_IN_MASK	(0x1F << 5)
 #define LDOSRAM_VOLT_CTRL_OVERRIDE	0x0401040f
@@ -125,9 +114,10 @@
 /* CONTROL_EFUSE_2 */
 #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1		0x00ffc000
 
-#define MMC1_PWRDNZ					(1 << 26)
-#define MMC1_PBIASLITE_PWRDNZ				(1 << 22)
-#define MMC1_PBIASLITE_VMODE				(1 << 21)
+#define SDCARD_PWRDNZ					(1 << 26)
+#define SDCARD_BIAS_HIZ_MODE				(1 << 25)
+#define SDCARD_BIAS_PWRDNZ				(1 << 22)
+#define SDCARD_PBIASLITE_VMODE				(1 << 21)
 
 #ifndef __ASSEMBLY__
 
@@ -136,32 +126,117 @@ struct s32ktimer {
 	unsigned int s32k_cr;	/* 0x10 */
 };
 
-struct omap4_sys_ctrl_regs {
-	unsigned int pad1[129];
-	unsigned int control_id_code;			/* 0x4A002204 */
-	unsigned int pad11[22];
-	unsigned int control_std_fuse_opp_bgap;		/* 0x4a002260 */
-	unsigned int pad2[47];
-	unsigned int control_ldosram_iva_voltage_ctrl;	/* 0x4A002320 */
-	unsigned int control_ldosram_mpu_voltage_ctrl;	/* 0x4A002324 */
-	unsigned int control_ldosram_core_voltage_ctrl;	/* 0x4A002328 */
-	unsigned int pad3[260277];
-	unsigned int control_pbiaslite;			/* 0x4A100600 */
-	unsigned int pad4[63];
-	unsigned int control_efuse_1;			/* 0x4A100700 */
-	unsigned int control_efuse_2;			/* 0x4A100704 */
+#define DEVICE_TYPE_SHIFT 0x6
+#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
+#define DEVICE_GP 0x3
+
+struct omap_sys_ctrl_regs {
+	u32 pad0[77]; /* 0x4A002000 */
+	u32 control_status; /* 0x4A002134 */
+	u32 pad1[794]; /* 0x4A002138 */
+	u32 control_paconf_global; /* 0x4A002DA0 */
+	u32 control_paconf_mode;  /* 0x4A002DA4 */
+	u32 control_smart1io_padconf_0; /* 0x4A002DA8 */
+	u32 control_smart1io_padconf_1; /* 0x4A002DAC */
+	u32 control_smart1io_padconf_2; /* 0x4A002DB0 */
+	u32 control_smart2io_padconf_0; /* 0x4A002DB4 */
+	u32 control_smart2io_padconf_1; /* 0x4A002DB8 */
+	u32 control_smart2io_padconf_2; /* 0x4A002DBC */
+	u32 control_smart3io_padconf_0; /* 0x4A002DC0 */
+	u32 control_smart3io_padconf_1; /* 0x4A002DC4 */
+	u32 pad2[14];
+	u32 control_pbias; /* 0x4A002E00 */
+	u32 control_i2c_0; /* 0x4A002E04 */
+	u32 control_camera_rx; /* 0x4A002E08 */
+	u32 control_hdmi_tx_phy; /* 0x4A002E0C */
+	u32 control_uniportm; /* 0x4A002E10 */
+	u32 control_dsiphy; /* 0x4A002E14 */
+	u32 control_mcbsplp; /* 0x4A002E18 */
+	u32 control_usb2phycore; /* 0x4A002E1C */
+	u32 control_hdmi_1; /*0x4A002E20*/
+	u32 control_hsi; /*0x4A002E24*/
+	u32 pad3[2];
+	u32 control_ddr3ch1_0; /*0x4A002E30*/
+	u32 control_ddr3ch2_0; /*0x4A002E34*/
+	u32 control_ddrch1_0;	/*0x4A002E38*/
+	u32 control_ddrch1_1;	/*0x4A002E3C*/
+	u32 control_ddrch2_0;	/*0x4A002E40*/
+	u32 control_ddrch2_1;	/*0x4A002E44*/
+	u32 control_lpddr2ch1_0; /*0x4A002E48*/
+	u32 control_lpddr2ch1_1; /*0x4A002E4C*/
+	u32 control_ddrio_0;  /*0x4A002E50*/
+	u32 control_ddrio_1;  /*0x4A002E54*/
+	u32 control_ddrio_2;  /*0x4A002E58*/
+	u32 control_hyst_1; /*0x4A002E5C*/
+	u32 control_usbb_hsic_control; /*0x4A002E60*/
+	u32 control_c2c; /*0x4A002E64*/
+	u32 control_core_control_spare_rw; /*0x4A002E68*/
+	u32 control_core_control_spare_r; /*0x4A002E6C*/
+	u32 control_core_control_spare_r_c0; /*0x4A002E70*/
+	u32 control_srcomp_north_side; /*0x4A002E74*/
+	u32 control_srcomp_south_side; /*0x4A002E78*/
+	u32 control_srcomp_east_side; /*0x4A002E7C*/
+	u32 control_srcomp_west_side; /*0x4A002E80*/
+	u32 control_srcomp_code_latch; /*0x4A002E84*/
+	u32 pad4[3680198];
+	u32 control_smart1nopmio_padconf_0; /* 0x4AE0CDA0 */
+	u32 control_smart1nopmio_padconf_1; /* 0x4AE0CDA4 */
+	u32 control_padconf_mode; /* 0x4AE0CDA8 */
+	u32 control_xtal_oscillator; /* 0x4AE0CDAC */
+	u32 control_i2c_2; /* 0x4AE0CDB0 */
+	u32 control_ckobuffer; /* 0x4AE0CDB4 */
+	u32 control_wkup_control_spare_rw; /* 0x4AE0CDB8 */
+	u32 control_wkup_control_spare_r; /* 0x4AE0CDBC */
+	u32 control_wkup_control_spare_r_c0; /* 0x4AE0CDC0 */
+	u32 control_srcomp_east_side_wkup; /* 0x4AE0CDC4 */
+	u32 control_efuse_1; /* 0x4AE0CDC8 */
+	u32 control_efuse_2; /* 0x4AE0CDCC */
+	u32 control_efuse_3; /* 0x4AE0CDD0 */
+	u32 control_efuse_4; /* 0x4AE0CDD4 */
+	u32 control_efuse_5; /* 0x4AE0CDD8 */
+	u32 control_efuse_6; /* 0x4AE0CDDC */
+	u32 control_efuse_7; /* 0x4AE0CDE0 */
+	u32 control_efuse_8; /* 0x4AE0CDE4 */
+	u32 control_efuse_9; /* 0x4AE0CDE8 */
+	u32 control_efuse_10; /* 0x4AE0CDEC */
+	u32 control_efuse_11; /* 0x4AE0CDF0 */
+	u32 control_efuse_12; /* 0x4AE0CDF4 */
+	u32 control_efuse_13; /* 0x4AE0CDF8 */
 };
 
-struct control_lpddr2io_regs {
-	unsigned int control_lpddr2io1_0;
-	unsigned int control_lpddr2io1_1;
-	unsigned int control_lpddr2io1_2;
-	unsigned int control_lpddr2io1_3;
-	unsigned int control_lpddr2io2_0;
-	unsigned int control_lpddr2io2_1;
-	unsigned int control_lpddr2io2_2;
-	unsigned int control_lpddr2io2_3;
-};
+/* Output impedance control */
+#define ds_120_ohm	0x0
+#define ds_60_ohm	0x1
+#define ds_45_ohm	0x2
+#define ds_30_ohm	0x3
+#define ds_mask		0x3
+
+/* Slew rate control */
+#define sc_slow		0x0
+#define sc_medium	0x1
+#define sc_fast		0x2
+#define sc_na		0x3
+#define sc_mask		0x3
+
+/* Target capacitance control */
+#define lb_5_12_pf	0x0
+#define lb_12_25_pf	0x1
+#define lb_25_50_pf	0x2
+#define lb_50_80_pf	0x3
+#define lb_mask		0x3
+
+#define usb_i_mask	0x7
+
+#define DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN   0x80828082
+#define DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN 0x82828200
+#define DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL 0x8421
+#define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084
+#define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000
+
+#define EFUSE_1 0x45145100
+#define EFUSE_2 0x45145100
+#define EFUSE_3 0x45145100
+#define EFUSE_4 0x45145100
 #endif /* __ASSEMBLY__ */
 
 /*
@@ -169,7 +244,7 @@ struct control_lpddr2io_regs {
  * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
  * at 0x40304000(EMU base) so that our code works for both EMU and GP
  */
-#define NON_SECURE_SRAM_START	0x40304000
+#define NON_SECURE_SRAM_START	0x40300000
 #define NON_SECURE_SRAM_END	0x40320000	/* Not inclusive */
 /* base address for indirect vectors (internal boot mode) */
 #define SRAM_ROM_VECT_BASE	0x4031F000