diff options
| author | Peng Fan <peng.fan@nxp.com> | 2021-08-07 16:00:35 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2021-08-09 14:46:50 +0200 |
| commit | 9ef89ea9b077094c33e483d8a826f0914d395ac4 (patch) | |
| tree | c876df90cad26c8b91887ac8b7e1016ac8fed294 /arch/arm/include/asm/arch-imx8ulp/ddr.h | |
| parent | c17f5935cf5f9decdbe5ac59662f8ca2a1b7efe2 (diff) | |
arm: imx: basic i.MX8ULP support
Add basic i.MX8ULP support
For the MMU part, Using a simple way the calculate the MMU size to avoid
default heavy calcaulation. And align address and size in the table
settings to 2MB or 4GB as much as possible. So we can reduce the 4K page
allocations in MMU table which will spends much time in create the
page table
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch/arm/include/asm/arch-imx8ulp/ddr.h')
| -rw-r--r-- | arch/arm/include/asm/arch-imx8ulp/ddr.h | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-imx8ulp/ddr.h b/arch/arm/include/asm/arch-imx8ulp/ddr.h new file mode 100644 index 0000000000..4544431b05 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8ulp/ddr.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +#ifndef __ASM_ARCH_IMX8ULP_DDR_H +#define __ASM_ARCH_IMX8ULP_DDR_H + +#include <asm/io.h> +#include <asm/types.h> + +struct dram_cfg_param { + unsigned int reg; + unsigned int val; +}; + +struct dram_timing_info2 { + /* ddr controller config */ + struct dram_cfg_param *ctl_cfg; + unsigned int ctl_cfg_num; + /* pi config */ + struct dram_cfg_param *pi_cfg; + unsigned int pi_cfg_num; + /* phy freq1 config */ + struct dram_cfg_param *phy_f1_cfg; + unsigned int phy_f1_cfg_num; + /* phy freq2 config */ + struct dram_cfg_param *phy_f2_cfg; + unsigned int phy_f2_cfg_num; + /* initialized drate table */ + unsigned int fsp_table[3]; +}; + +extern struct dram_timing_info2 dram_timing; + +int ddr_init(struct dram_timing_info2 *dram_timing); + +#endif |