diff options
| author | Tom Rini <trini@konsulko.com> | 2016-02-24 14:25:54 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-02-24 18:44:15 -0500 |
| commit | e1417c7b66f4e0051a3aa242f655e85c1c96eef2 (patch) | |
| tree | 2ce107939d41320686cd367bbf882ed53ef6e6c9 /arch/arm/cpu/armv8/fsl-layerscape/soc.c | |
| parent | 20434c8a0b9f6ff4a14d65fdb24c189f283412b2 (diff) | |
| parent | a08b1921b4a477abe1ac4482fae9ec4bcb3cd27e (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/soc.c')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/soc.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 7ff01481be..213ce3a824 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -213,6 +213,24 @@ static void erratum_a009929(void) #endif } +/* + * This erratum requires setting a value to eddrtqcr1 to optimal + * the DDR performance. The eddrtqcr1 register is in SCFG space + * of LS1043A and the offset is 0x157_020c. + */ +#if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \ + && defined(CONFIG_SYS_FSL_ERRATUM_A008514) +#error A009660 and A008514 can not be both enabled. +#endif + +static void erratum_a009660(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009660 + u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c; + out_be32(eddrtqcr1, 0x63b20042); +#endif +} + void fsl_lsch2_early_init_f(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; @@ -238,6 +256,7 @@ void fsl_lsch2_early_init_f(void) /* Erratum */ erratum_a009929(); + erratum_a009660(); } #endif |