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| author | Tom Rini <trini@konsulko.com> | 2016-07-26 17:34:28 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-07-26 17:34:28 -0400 |
| commit | 9c7a0a600bfc8741e2941ce9bb965f2e77d6bbea (patch) | |
| tree | a475756b966b614ad545299fa82dfd89c863aab8 /arch/arm/cpu/armv8/fsl-layerscape/cpu.c | |
| parent | c3c9fd31bad80ead1682de917e27fa6073eae02b (diff) | |
| parent | 8401c7103d73b4010df95bf8bc79a60f378f1e50 (diff) | |
Merge git://git.denx.de/u-boot-fsl-qoriq
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/cpu.c')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 7a2ec6bf59..e12b773550 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -145,11 +145,14 @@ static inline void final_mmu_setup(void) set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL), MEMORY_ATTRIBUTES); /* - * MMU is already enabled, just need to invalidate TLB to load the + * EL3 MMU is already enabled, just need to invalidate TLB to load the * new table. The new table is compatible with the current table, if * MMU somehow walks through the new table before invalidation TLB, * it still works. So we don't need to turn off MMU here. + * When EL2 MMU table is created by calling this function, MMU needs + * to be enabled. */ + set_sctlr(get_sctlr() | CR_M); } u64 get_page_table_size(void) @@ -309,7 +312,8 @@ int print_cpuinfo(void) printf("CPU%d(%s):%-4s MHz ", core, type == TY_ITYP_VER_A7 ? "A7 " : (type == TY_ITYP_VER_A53 ? "A53" : - (type == TY_ITYP_VER_A57 ? "A57" : " ")), + (type == TY_ITYP_VER_A57 ? "A57" : + (type == TY_ITYP_VER_A72 ? "A72" : " "))), strmhz(buf, sysinfo.freq_processor[core])); } printf("\n Bus: %-4s MHz ", |