diff options
| author | Marek Vasut <marek.vasut+renesas@mailbox.org> | 2023-09-17 16:08:35 +0200 |
|---|---|---|
| committer | Marek Vasut <marek.vasut+renesas@mailbox.org> | 2023-10-01 00:08:28 +0200 |
| commit | f3a163dc861b4ad6bc85d721a7f0017443b84de5 (patch) | |
| tree | a6f28192e7e7e00ba9447f12b6d5609b8db6ab27 | |
| parent | 8cf4d3faec924d5b672f93e6e8fdd92be243f317 (diff) | |
pinctrl: renesas: Add support for 1.8V/2.5V I/O voltage levels
Currently, the Renesas pin control driver supports pins that can switch
their I/O voltage levels between either 1.8V and 3.3V, or between 2.5V
and 3.3V. However, some SoCs have pins that can switch between 1.8V and
2.5V.
Add support for this by replacing the separate SH_PFC_PIN_CFG_IO_VOLTAGE
capability and voltage level flags by a 2-bit field, to cover three
possible I/O voltage switching options.
Ported from Linux kernel commit by Geert Uytterhoeven:
b88e733ac517 ("pinctrl: renesas: Add support for 1.8V/2.5V I/O voltage levels")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
| -rw-r--r-- | drivers/pinctrl/renesas/pfc.c | 9 | ||||
| -rw-r--r-- | drivers/pinctrl/renesas/sh_pfc.h | 20 |
2 files changed, 14 insertions, 15 deletions
diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c index f6e8dd9337..3ac25cbd08 100644 --- a/drivers/pinctrl/renesas/pfc.c +++ b/drivers/pinctrl/renesas/pfc.c @@ -798,7 +798,7 @@ static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin, return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH; case PIN_CONFIG_POWER_SOURCE: - return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE; + return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK; default: return false; @@ -814,6 +814,7 @@ static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin, int bit, ret; int idx = sh_pfc_get_pin_index(pfc, _pin); const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; + unsigned int mode, hi, lo; if (!sh_pfc_pinconf_validate(pfc, _pin, param)) return -ENOTSUPP; @@ -851,8 +852,12 @@ static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin, pocctrl = (void __iomem *)(uintptr_t)addr; + mode = pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK; + lo = mode <= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 1800 : 2500; + hi = mode >= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 3300 : 2500; + val = sh_pfc_read_raw_reg(pocctrl, 32); - if (arg == ((pin->configs & SH_PFC_PIN_VOLTAGE_18_25) ? 2500 : 3300)) + if (arg == hi) val |= BIT(bit); else val &= ~BIT(bit); diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index bf40944053..e6c2117612 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -26,19 +26,13 @@ enum { #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3) #define SH_PFC_PIN_CFG_PULL_UP_DOWN (SH_PFC_PIN_CFG_PULL_UP | \ SH_PFC_PIN_CFG_PULL_DOWN) -#define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4) -#define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5) - -#define SH_PFC_PIN_VOLTAGE_18_33 (0 << 6) -#define SH_PFC_PIN_VOLTAGE_25_33 (1 << 6) -#define SH_PFC_PIN_VOLTAGE_18_25 (2 << 6) - -#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \ - SH_PFC_PIN_VOLTAGE_18_33) -#define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \ - SH_PFC_PIN_VOLTAGE_25_33) -#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_25 (SH_PFC_PIN_CFG_IO_VOLTAGE | \ - SH_PFC_PIN_VOLTAGE_18_25) + +#define SH_PFC_PIN_CFG_IO_VOLTAGE_MASK GENMASK(5, 4) +#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_25 (1 << 4) +#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 (2 << 4) +#define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33 (3 << 4) + +#define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 6) #define SH_PFC_PIN_CFG_NO_GPIO (1 << 31) |