diff options
| author | Roger Quadros <rogerq@kernel.org> | 2024-02-06 16:02:51 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-02-13 15:38:11 -0500 |
| commit | ef473d541d8a5453ce66b3c72f7e5577a7ea6aff (patch) | |
| tree | f67c5628a47c554be7febb6518114443219a3cb3 | |
| parent | b12883fc38adca78800f7a60f3f2f3053635d598 (diff) | |
memory: ti-gpmc: Fix lock up at A53 SPL during NAND boot on AM64-EVM
AM64 ES2.0 bootrom seems to enable WAIT0EDGEDETECTION interrupt.
This causes a lockup at A53 SPL when accessing NAND controller
or ELM registers.
A good option would be to softrest GPMC block at probe
but this cannot be done for AM64 as SOFTRESET bit is marked
as reserved in SYSCONFIG register.
Fix the issue by disabling all IRQs at probe.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
| -rw-r--r-- | drivers/memory/ti-gpmc.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/memory/ti-gpmc.c b/drivers/memory/ti-gpmc.c index 0b8674339e..8877b8f438 100644 --- a/drivers/memory/ti-gpmc.c +++ b/drivers/memory/ti-gpmc.c @@ -1196,6 +1196,12 @@ static int gpmc_probe(struct udevice *dev) gpmc_cfg = (struct gpmc *)priv->base; gpmc_base = priv->base; + /* + * Disable all IRQs as some bootroms might leave them enabled + * and that will cause a lock-up later + */ + gpmc_write_reg(GPMC_IRQENABLE, 0); + priv->l3_clk = devm_clk_get(dev, "fck"); if (IS_ERR(priv->l3_clk)) return PTR_ERR(priv->l3_clk); |