diff options
| author | Marek Vasut <marex@denx.de> | 2023-12-07 18:50:31 +0100 |
|---|---|---|
| committer | Fabio Estevam <festevam@denx.de> | 2023-12-14 15:29:08 -0300 |
| commit | c4cc14433dcdb9480eb496541dc7960f7eb718c0 (patch) | |
| tree | 62972aa764611db96793992c3985b47feefb5cc3 | |
| parent | f4d15df831955cd51dc238a39d06bd61f43fce2c (diff) | |
ARM: imx: Force DRAM regulators into FPWM mode on Data Modul i.MX8M Plus eDM SBC
In case the Buck5 and Buck6 regulators which supply DRAM Vdd1 and Vdd2/Vddq
respectively operate in automatic PWM/PFM mode, the DRAM EDAC detects more
correctable errors than if the regulators operate in forced PWM only mode.
Force DRAM regulators to forced PWM mode only to stop tempting the DRAM.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
| -rw-r--r-- | board/data_modul/imx8mp_edm_sbc/spl.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/board/data_modul/imx8mp_edm_sbc/spl.c b/board/data_modul/imx8mp_edm_sbc/spl.c index cfc4b65e0f..a3600c8568 100644 --- a/board/data_modul/imx8mp_edm_sbc/spl.c +++ b/board/data_modul/imx8mp_edm_sbc/spl.c @@ -68,6 +68,11 @@ int data_modul_imx_edm_sbc_board_power_init(void) /* To avoid timing risk from SoC to ARM, increase VDD_ARM to OD voltage 0.95V */ pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1c); + /* DRAM Vdd1 always FPWM */ + pmic_reg_write(dev, PCA9450_BUCK5CTRL, 0x0d); + /* DRAM Vdd2/Vddq always FPWM */ + pmic_reg_write(dev, PCA9450_BUCK6CTRL, 0x0d); + /* Set LDO4 and CONFIG2 to enable the I2C level translator. */ pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x59); pmic_reg_write(dev, PCA9450_CONFIG2, 0x1); |