diff options
| author | Marek Behún <kabel@kernel.org> | 2022-07-27 15:00:27 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2022-07-29 13:55:52 +0200 |
| commit | b2d7619e46aa414cba14a1705892b7e249468d6f (patch) | |
| tree | 8c6ee3bbcb0c078f43b4286c097b929523454c14 | |
| parent | 162311637da4170212f7a9ca4bddbc9374af1d6a (diff) | |
arm: mvebu: turris_omnia: Fix mpp26 pin name and comment
There is a bug in Turris Omnia's schematics, whereupon the MPP[26] pin,
which is routed to CN11 pin header, is documented as SPI CS1, but
MPP[26] pin does not support this function. Instead it controls chip
select 2 if in "spi0" mode.
Fix the name of the pin node in pinctrl node and fix the comment in SPI
node.
Signed-off-by: Marek Behún <kabel@kernel.org>
| -rw-r--r-- | arch/arm/dts/armada-385-turris-omnia.dts | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/dts/armada-385-turris-omnia.dts b/arch/arm/dts/armada-385-turris-omnia.dts index 9980a854e3..0be55f8bf6 100644 --- a/arch/arm/dts/armada-385-turris-omnia.dts +++ b/arch/arm/dts/armada-385-turris-omnia.dts @@ -488,7 +488,7 @@ marvell,function = "spi0"; }; - spi0cs1_pins: spi0cs1-pins { + spi0cs2_pins: spi0cs2-pins { marvell,pins = "mpp26"; marvell,function = "spi0"; }; @@ -523,7 +523,7 @@ }; }; - /* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */ + /* MISO, MOSI, SCLK and CS2 are routed to pin header CN11 */ }; &uart0 { |