diff options
| author | Loic Poulain <loic.poulain@linaro.org> | 2022-03-31 12:39:37 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2022-04-21 12:44:23 +0200 |
| commit | 85d0580e684c74dcb0a90aa0c010006cda40af44 (patch) | |
| tree | c2c32d8381100c8cb890dc904ca496daaf08d3d0 | |
| parent | 22bfaa1f673ab5442dfb9778eea4c9a18dee42d0 (diff) | |
imx8ulp: clock: Fix lcd clock algo
The div loop uses reassign and reuse parent_rate, which causes
the parent rate reference to be wrong after the first loop, the
resulting clock becomes incorrect for div != 1.
Fixes: 829e06bf4175 ("imx8ulp: clock: Add MIPI DSI clock and DCNano clock")
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
| -rw-r--r-- | arch/arm/mach-imx/imx8ulp/clock.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c index 3e71a4f6c3..3e88f4633c 100644 --- a/arch/arm/mach-imx/imx8ulp/clock.c +++ b/arch/arm/mach-imx/imx8ulp/clock.c @@ -440,10 +440,9 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz) debug("PLL4 rate %ukhz\n", pll4_rate); for (pfd = 12; pfd <= 35; pfd++) { - parent_rate = pll4_rate; - parent_rate = parent_rate * 18 / pfd; - for (div = 1; div <= 64; div++) { + parent_rate = pll4_rate; + parent_rate = parent_rate * 18 / pfd; parent_rate = parent_rate / div; for (pcd = 0; pcd < 8; pcd++) { |