diff options
| author | Ashok Reddy Soma <ashok.reddy.soma@amd.com> | 2023-07-19 02:49:12 -0600 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2023-07-21 09:00:39 +0200 |
| commit | 7a480fd995e279dd883b9e4e24741f9c71d66143 (patch) | |
| tree | 846209b84de10786e055e7a6de55a74d5e9c89db | |
| parent | 3fb4ef7d39abbb2f8f6cd349e4af11082bf8c8c4 (diff) | |
clk: zynqmp: Add set_rate support for gem rx and tsu clks
gem0_rx till gem3_rx and gem_tsu are missing from set rate function.
Add them, so that they can be set from pmu firmware via clock framework.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230719084912.30209-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
| -rw-r--r-- | drivers/clk/clk_zynqmp.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c index 8320d49184..53327cf9ad 100644 --- a/drivers/clk/clk_zynqmp.c +++ b/drivers/clk/clk_zynqmp.c @@ -719,6 +719,8 @@ static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate) switch (id) { case gem0_ref ... gem3_ref: case gem0_tx ... gem3_tx: + case gem0_rx ... gem3_rx: + case gem_tsu: case qspi_ref ... can1_ref: case usb0_bus_ref ... usb3_dual_ref: return zynqmp_clk_set_peripheral_rate(priv, id, |